JPS58103142A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS58103142A JPS58103142A JP20212681A JP20212681A JPS58103142A JP S58103142 A JPS58103142 A JP S58103142A JP 20212681 A JP20212681 A JP 20212681A JP 20212681 A JP20212681 A JP 20212681A JP S58103142 A JPS58103142 A JP S58103142A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- resin
- nozzle
- gas
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 238000000034 method Methods 0.000 claims abstract description 9
- 238000003825 pressing Methods 0.000 claims abstract description 5
- 239000000463 material Substances 0.000 claims description 11
- 239000012530 fluid Substances 0.000 claims description 5
- 229920005989 resin Polymers 0.000 abstract description 15
- 239000011347 resin Substances 0.000 abstract description 15
- 239000007787 solid Substances 0.000 abstract description 5
- 238000000465 moulding Methods 0.000 abstract description 2
- 239000007789 gas Substances 0.000 abstract 3
- 229920001721 polyimide Polymers 0.000 abstract 2
- 239000009719 polyimide resin Substances 0.000 abstract 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 abstract 1
- 230000002349 favourable effect Effects 0.000 abstract 1
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000011824 nuclear material Substances 0.000 description 3
- ZSLUVFAKFWKJRC-IGMARMGPSA-N 232Th Chemical compound [232Th] ZSLUVFAKFWKJRC-IGMARMGPSA-N 0.000 description 2
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- 229910052776 Thorium Inorganic materials 0.000 description 2
- 239000011162 core material Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000005022 packaging material Substances 0.000 description 2
- 238000007493 shaping process Methods 0.000 description 2
- 229920002050 silicone resin Polymers 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 101000802779 Rattus norvegicus Alpha-1-macroglobulin Proteins 0.000 description 1
- 241000220317 Rosa Species 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000011093 chipboard Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000006023 eutectic alloy Substances 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 230000005258 radioactive decay Effects 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
（υ 発明の技術分野
本発明は半導体装置の製造方法、特に半導体テッグ面上
の保躾皮膜の整形方法に関す。DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for shaping a maintenance film on a semiconductor TEG surface.
（２）技術の背景
ダイナ建ｖり２ンダム アタ令スメモリ（ｄｙｅ闘ｍｌ
Ｃｒａｎｄｍ ａｃｃｅｓｓ ｍｅｍｏｒｙ ：以下Ｄ
ＲＡＭと略称する）及び電荷納会素子（ｃｈａｒｇ＠ｃ
ｏｕｐ１番ｄ ｄｅ−マＩＣ・：以下ＣＣＤと略称する
）のソフトエラー（，１
が電離作用の強要放射＊によって発生することが知られ
ている。(2) Technical background
Crandm access memory: Hereinafter D
(abbreviated as RAM) and charge storage element (charg@c
It is known that soft errors (,1) of oup1 d de -ma IC (hereinafter abbreviated as CCD) occur due to forced radiation* of ionizing action.
すなわち、ＤＲＡＭのパッケージ材料等に微量に存在す
るクジン（し）やトリウム（Ｔｈ）が放射性崩壊する際
にアルファ粒子が放出される：とのアルファ粒子が＃Ｄ
ＲＡＭのチップ表面を透過する際に記憶ノード付近に多
数の電子−正孔対を形成して記憶デー−を逆転してソフ
トエ２−となるものである。In other words, alpha particles are released during radioactive decay of trace amounts of thorium and thorium present in DRAM packaging materials.
When transmitted through the RAM chip surface, a large number of electron-hole pairs are formed in the vicinity of the storage node and the stored data is reversed, resulting in a soft data 2-.
仁のソフトエラーは、ＤＲＡＭが高集積化され、各メモ
リーセルの電荷蓄積量が少くなるに伴って顕在化して来
九が、その原因であるαやＴｈは該デバイス中のパッケ
ージ材料特に成形樹脂中のフィラーに多く含まれている
。Soft errors have become more apparent as DRAMs become more highly integrated and the amount of charge stored in each memory cell decreases.The causes of soft errors, α and Th, are caused by the packaging material in the device, especially the molding resin. Contains a lot of filler inside.
（３）従来技術と問題点
前記のパッケージ材料中のｕ＋Ｔｂに起因するソフトエ
ラーを防止する目的の従来技術による半導体装置の構造
の一例の水平断面図を第１図（ａ）に、垂直断面図を第
１図（ｂ）Ｋ示す。なお断面に現われないワイヤを付記
している。図において、ＩＦｉ手導体チップ、２はチッ
プｌを支持する基板、３は鉄（Ｆ・）ニッケル（Ｎ１）
合金に銀（ムｇ）もしくは金ＣＡｕ）め２１ｍ１Ｖｒ施
し丸ものである。半導体テップｌけ基板２ＫＡｕ−３１
共晶會金４等によりｌンダイングされ、又、チップ１の
パッドと外部電子３とはワイヤ５によ少飯続される。(3) Prior art and problems FIG. 1(a) is a horizontal sectional view of an example of the structure of a semiconductor device according to the prior art for the purpose of preventing soft errors caused by u+Tb in the package material, and a vertical sectional view is shown in FIG. is shown in FIG. 1(b)K. Note that wires that do not appear in the cross section are also noted. In the figure, the IFi conductor chip, 2 is the substrate that supports the chip l, 3 is iron (F・) nickel (N1)
The alloy is coated with silver (mug) or gold (CAu) and is rounded with 21m1Vr. Semiconductor chip board 2KAu-31
The pads of the chip 1 and the external electrons 3 are connected to each other by a wire 5.
本従来技術例においては、半導体チｙ７′ｘ上にポリイ
ンド系樹脂もしくはシリコーン樹脂等よｐなる皮膜６を
アルファ１ｍ阻止の目的で設けた後に、エポキシ偽′脂
によルパッケージ７を形成している。In this prior art example, after a film 6 made of polyindo resin or silicone resin is provided on the semiconductor chip y7'x for the purpose of blocking alpha 1m, a package 7 is formed with epoxy resin. There is.
前記のポリインド系樹脂もしくはシリコーン樹脂等より
なる皮ｊＫ６がアルファ線を阻止する友めには少くとも
１００μ富の厚さを必豐とする。しかるに粘性の大きめ
＃軒を滴下等の方法によってチップｌ上に付着ぜしめる
とき、チップ面上をほぼ均一の厚さに被覆する仁となく
、滴下位置において厚く、チｙ ７’ １ ｆ） Ｊｌ
１辺においては薄く被覆する九めに、この材料を固化し
たとき、彫１図（ｂ）に皮ｌ１４６として示す如く、中
央付近においては厚く、周辺においては薄い皮膜となり
１周辺付近においては目的とするアルファ！ＩＩＩＵ止
効果が得られない結果となる・
チップ１０周辺部分における皮［１６の厚さが、１００
ｋｇ以上となる様に、中央部分が厚い従来の形状の１１
で樹脂量を増加して全体を厚くすると１１は、バラケー
ジ７の肉厚がチップ１の中央部分において過度に薄くな
るという問題を惹起する・（４） 発明の目的
本発明は、半導体チップ面を流動性を有する物質で被覆
し、核物質を固化せしめて該チップ面に■態皮膜を形成
する半導体装置の製造方法において、工業的に容易に実
施できる該皮膜の整形方法を提供することを目的とする
。In order for the skin JK6 made of the above-mentioned polyindo resin or silicone resin to block alpha rays, it must have a thickness of at least 100 μm. However, when a highly viscous #eave is adhered onto a chip by a method such as dropping, there is no layer that covers the chip surface to an almost uniform thickness, and it is thick at the dropping position.
When this material is solidified, it is thicker near the center and thinner at the periphery, and when this material is solidified, it becomes thicker near the center and thinner at the periphery, and the area around the periphery becomes thinner. Alpha to do! As a result, the IIIU prevention effect cannot be obtained. The thickness of the skin [16] around the tip 10 is 100 mm.
11 of the conventional shape with a thick center part so that it weighs more than 11 kg.
If the amount of resin is increased to make the whole chip 11 thicker, a problem arises in that the wall thickness of the rose cage 7 becomes excessively thin in the central part of the chip 1. An object of the present invention is to provide a method for shaping a film that can be easily carried out industrially in a method for manufacturing a semiconductor device in which a core material is coated with a fluid substance and a nuclear material is solidified to form a film in the form of a state on the chip surface. shall be.
（５）発明の構成
本発明の前記目的は、前記チップ面の中央部において前
記流動性を有する物質に対し圧力を加えつつ核物質を固
化することによｐ達成される。(5) Structure of the Invention The above object of the present invention is achieved by solidifying the nuclear material while applying pressure to the fluid material at the center of the chip surface.
（６）発明の実施例
以下本発明を実施例によシ図面を参照して具体的Ｋａ明
する。(6) Embodiments of the Invention The present invention will now be explained in detail by way of embodiments and with reference to the drawings.
第２図（１）乃至伽）は本発明の第一の実施例を示す模
式図である。すなわち半導体テップ】１が第２図（（転
）ｋ示す如くノズル１２下に置かれ、ノズル１２より流
動性を有する物質、例えばポリインド系樹脂１３を滴下
する。滴下され九樹脂は第２図（ｂ）Ｋ符号１４で示す
如く中央部が厚く周辺部が薄い山形をなす。本実施例に
おいては、第２図（Ｃ） Ｋ示す如くこのチップ１１を
加熱した窒素（Ｎ黛） ｔ−噴出するノズル１５の直下
に送シ、ｔシブ１１の中央部分に加熱Ｎ、を吹きつける
。このＮ、により圧力が加えられる結果、樹脂は符号１
６で示す如く周辺に流動してチップ１１０周辺部におい
て４所要の厚さを保つこととなる。この状態を続けつつ
樹脂を固化することによって、＠２図（ｄ）において符
号１７で示す如く、チップ１１の所要範囲において所要
の厚さを有するポリインド系樹脂による固態皮Ｊ［を得
る。FIGS. 2(1) to 2) are schematic diagrams showing a first embodiment of the present invention. That is, the semiconductor tip 1 is placed under the nozzle 12 as shown in FIG. b) It forms a mountain shape with a thick central part and a thin peripheral part as shown by K 14. In this embodiment, as shown in FIG. Directly below the nozzle 15, heated N is sprayed onto the central part of the t-sive 11.As a result of the pressure applied by this N, the resin becomes 1
As shown by 6, the liquid flows to the periphery and maintains the required thickness at the periphery of the chip 110. By continuing this state and solidifying the resin, a solid skin J made of polyindo resin having a required thickness in a required range of the chip 11 is obtained, as shown by reference numeral 17 in Figure 2 (d).
第３図（ａ）乃至（ｄ）は本発明の第二の実施例を示す
模式図である・本実施例においては、第一の実施例と同
様にポリインド系樹脂をチップ１１に滴下し、第３図（
ｃ）Ｋ示す如く押え具１８によってチップ１１の中央部
分において樹脂に圧力を加える０この状態において樹脂
を固化することによ〉第３図（ｄ）ｋおいて符号１９で
示す如く所要の固層皮膜を＃る。FIGS. 3(a) to 3(d) are schematic diagrams showing a second embodiment of the present invention. In this embodiment, polyindo resin is dropped onto the chip 11 as in the first embodiment, Figure 3 (
c) By applying pressure to the resin in the central part of the chip 11 with the presser 18 as shown in K, by solidifying the resin in this state, a required solid layer is formed as shown in FIG. 3(d)k. Coat the film.
（７） 発明の効果
本発明は半導体チップ面を流動性を有する状態の樹脂等
の物質で被覆し、核物質を固化せしめて皺ｔッグＩＩＫ
固態皮膜を形成するに際して、チップ面の中央部におい
て該物質に対し圧力を加えつつ核物質を固化するととＫ
よシ、所要の形状特に厚さを有する固層皮膜を形成する
半導体装置の製造方法を提供するものであって、皺チッ
プに形成されたＤＲＡＭ等のソフトエラーの防止等、半
導体装置の１頼性向上に効果が大きく、かつ工業的に容
重に奥施し得る利点を有する。(7) Effects of the Invention The present invention covers the surface of a semiconductor chip with a material such as resin in a fluid state, solidifies the core material, and forms a wrinkled tag IIK.
When forming a solid film, solidify the nuclear material while applying pressure to the material at the center of the chip surface.
The present invention provides a method for manufacturing a semiconductor device that forms a solid layer film having a desired shape, especially thickness, and is one of the most important features of semiconductor devices, such as preventing soft errors in DRAMs and other devices formed on wrinkled chips. It has the advantage of being highly effective in improving properties and being industrially applicable.
第Ｚｌｅｌ（１ｍ）は従来技術による半導体装置の一例
を示す水平断面図、第１図（ｂ）＃′ｉその垂直断面図
、第２図（ａ）乃至（ｄ）は本発明の一実施例、第３図
体）乃至（句は本発明の他の実−例を示す。
図において、ＩＦｉ半導体チップ、２は基板、３Ｕ外部
端子、４はＡｕ−８１共晶合金、５はワイヤ、６は皮膜
、７けバタケージ、ＩＩＨ半導体チップ、１２はノズル
、１３．１４及び１６は樹脂の形状、１５はノズル、１
７は皮膜、１８は押え具、１９は皮膜を示す。
（ｔス、ン （ｂ〕
Ｃｏ （ｄ）′Ｉ！
３ 図No. Zelel (1m) is a horizontal sectional view showing an example of a semiconductor device according to the prior art, FIG. 1(b) is a vertical sectional view thereof, and FIGS. , Figure 3) to (phrases indicate other examples of the present invention. In the figure, 2 is an IFi semiconductor chip, 2 is a substrate, 3U external terminals, 4 is an Au-81 eutectic alloy, 5 is a wire, and 6 is a Film, 7-beam cage, IIH semiconductor chip, 12 is a nozzle, 13, 14 and 16 are resin shapes, 15 is a nozzle, 1
7 is a film, 18 is a presser, and 19 is a film. (tsu, n (b)
Co (d)′I!
3 diagram
Claims (1)
を固化せしめて該チップ面に動態皮膜を形成する半導体
装置の製造方法において、鋏チＶプ面の中央部において
＃流動性を有する物質に対し圧力を加えつつ皺物質を固
化することを特徴とする半導体装置の製造方法。In a method for manufacturing a semiconductor device in which the semiconductor chip side is coated with a fluid material and the material is solidified to form a dynamic film on the chip surface, # the fluid material is coated in the central part of the scissors chip V surface. A method for manufacturing a semiconductor device, characterized by solidifying a wrinkled material while applying pressure to the material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20212681A JPS58103142A (en) | 1981-12-15 | 1981-12-15 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20212681A JPS58103142A (en) | 1981-12-15 | 1981-12-15 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58103142A true JPS58103142A (en) | 1983-06-20 |
Family
ID=16452388
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20212681A Pending JPS58103142A (en) | 1981-12-15 | 1981-12-15 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58103142A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100778816B1 (en) | 2005-05-19 | 2007-11-22 | 세이코 엡슨 가부시키가이샤 | Method of manufacturing microlens, microlens, optical film, screen for projection, projector system, electrooptical device and electronic equipment |
-
1981
- 1981-12-15 JP JP20212681A patent/JPS58103142A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100778816B1 (en) | 2005-05-19 | 2007-11-22 | 세이코 엡슨 가부시키가이샤 | Method of manufacturing microlens, microlens, optical film, screen for projection, projector system, electrooptical device and electronic equipment |
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