JPS58135A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS58135A JPS58135A JP56098565A JP9856581A JPS58135A JP S58135 A JPS58135 A JP S58135A JP 56098565 A JP56098565 A JP 56098565A JP 9856581 A JP9856581 A JP 9856581A JP S58135 A JPS58135 A JP S58135A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- film
- silicone
- thickness
- thin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 7
- 238000004519 manufacturing process Methods 0.000 title claims description 3
- 239000000463 material Substances 0.000 claims abstract description 26
- 239000010409 thin film Substances 0.000 claims abstract description 20
- 239000002904 solvent Substances 0.000 claims abstract description 8
- 238000000034 method Methods 0.000 claims description 11
- 239000007788 liquid Substances 0.000 claims description 4
- 239000011344 liquid material Substances 0.000 claims description 2
- 230000001681 protective effect Effects 0.000 claims description 2
- 239000010408 film Substances 0.000 abstract description 8
- 229920005989 resin Polymers 0.000 abstract description 7
- 239000011347 resin Substances 0.000 abstract description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 2
- 229910052710 silicon Inorganic materials 0.000 abstract 2
- 239000010703 silicon Substances 0.000 abstract 2
- 229920001296 polysiloxane Polymers 0.000 description 17
- 229920006268 silicone film Polymers 0.000 description 9
- 230000005260 alpha ray Effects 0.000 description 6
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000004080 punching Methods 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 229920002050 silicone resin Polymers 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85909—Post-treatment of the connector or wire bonding area
- H01L2224/8592—Applying permanent coating, e.g. protective coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、半導体装置の製造方法、例えばα線対策とし
て半導体チッ／の上に形成されゐシリコーン膜の如き保
■膜を、溶媒をはとんと含まない被覆材料をチク／上に
滴下し硬化するＫついて、滴下した材料の表面をほぼ平
らに形成する方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, for example, a protective film such as a silicone film formed on a semiconductor chip as a countermeasure against alpha rays, is coated with a coating material that does not contain any solvent. The present invention relates to a method for forming a substantially flat surface of a material onto which K is dropped and hardened.
Ｍｏｌ記憶装置（メモリ）が形成され九チッｌのメモリ
セル（記憶素子）およびセンス増幅器の配置され九領域
を、自然に存在する９ Ｍ ＠Ｖ （えだしＭは百方）
Ｏエネルギをもりα線から保験する丸め、チップの表面
を例えばシリコーン膜によって保藤することが行われる
。Mol storage device (memory) is formed and 9 areas where 9 chips of memory cells (memory elements) and sense amplifiers are arranged are naturally existing 9 M @V (M is in 100 directions)
Rounding is performed to protect the O energy from α rays, and the surface of the chip is coated with a silicone film, for example.
第１１１１には／皆ツケージ内に封止されたチＦ７”が
断面で示され、図において、ｌはテｙｆ１２はステー／
、３はリード、４はチッｌとリードを接続する配線、５
はモールド樹脂である。前記し九エネルギの１然界Ｏａ
線に対しメモリセルなどを十分保■するには、１００μ
ｓ＠変の厚さのシリコーン膜が必簀であるとされている
。No. 1111 shows a cross section of the hinge F7'' sealed in the cage, and in the figure, l is the tie f12 is the stay/
, 3 is the lead, 4 is the wiring connecting the chip and the lead, 5
is mold resin. The above-mentioned nine energy world Oa
In order to sufficiently protect memory cells etc. from the wire, 100μ
It is said that a silicone film with a thickness of s@ is required.
とζろで、第２図のチｙ７’ｌの平面図を参照すると、
図で点線で囲む部分がメモリセルなどの配置され九αｍ
ｌＫ敏感な領域６で、この領域上には１００声ｗｈｏ膜
厚のシリコーン膜が形成されることが望壜しい、なお、
α線に敏感な領域６以外の領域７は通常配線用電極が設
けられる領域である。If you refer to the plan view of y7'l in Figure 2,
The area surrounded by dotted lines in the figure is where memory cells, etc. are arranged.
In the lK sensitive region 6, it is desirable that a silicone film with a thickness of 100 tones be formed on this region.
Regions 7 other than the region 6 sensitive to alpha rays are regions where wiring electrodes are normally provided.
なお、領域６は第１図に４点着で囲って示す。Note that region 6 is shown surrounded by four points in FIG. 1.
α線対策用のシリコーン膜は、チッ７”ｌ上に数Ｚリグ
ラムのシリコーンを滴下し、次にチップを恒温槽に入れ
１５０℃〜２００℃の温度で数時間処理し、シリコーン
ｔ−硬化させることＫよりて形成される。そのとき、シ
リコーンｍａａ第１図に示す如き形状をとる。その理由
は、シリコーンはほとんど溶媒を含まず、そのほぼ１０
０％がシリコン樹脂であるから、シリコーンがチップ上
に滴下され九ときに表面張力によって第１図に示す如き
形状をとった４のが＊＆硬化されてもその最初の形状を
保つからである。The silicone film for α-ray protection is made by dropping several grammes of silicone onto a 7"l chip, then placing the chip in a constant temperature bath and treating it at a temperature of 150°C to 200°C for several hours to cure the silicone. At that time, silicone maa takes the shape shown in Figure 1.The reason is that silicone contains almost no solvent, and approximately 10
Since 0% is silicone resin, when the silicone is dropped onto the chip, it takes the shape shown in Figure 1 due to surface tension and retains its initial shape even after curing. .
このように形成され九シリコーン膜８が配！１４０近く
の線９で示す部分で１００μ調の厚さをもつとすると、
線１０で示す［８の中心部分の膜厚は４００μｍ程皺に
なる。The nine silicone films 8 formed in this way are arranged! Assuming that the part shown by line 9 near 140 has a thickness of 100μ,
The film thickness at the center of the line 10 [8] is wrinkled by about 400 μm.
ところで、チップが上記の如く処理された後、それは更
に樹脂モールド５によって被後される。By the way, after the chip is processed as described above, it is further covered with a resin mold 5.
このモールド５は、その厚さがチッｆｌの表面から測っ
て２．０−程度になるよう形成される。そうなると、シ
リコーンｌＩ８の頂上部分上の厚さのモールドでは十分
な防湿効果を発揮しえない、すなわち、線１０の部分の
厚さが、線９で示す部分と同様に１００μ講程度の厚さ
であることが必賛である。This mold 5 is formed so that its thickness is approximately 2.0 mm as measured from the surface of the chip. In this case, a mold having a thickness above the top portion of the silicone lI8 cannot exhibit a sufficient moisture-proofing effect.In other words, the thickness of the portion indicated by line 10 is approximately 100 μm thick, similar to the portion indicated by line 9. Certain things are essential.
本発明は、従来技術における上記の課題を解決すること
を目的とするもので、その目的を達成すべく、本願の発
明者は、シリコーンの如き溶媒をほとんど含まないα線
遮蔽材料をチップ上に滴下した後に、その材料の上に絶
縁性をもった薄膜をのせ、尚腋材料の表面がこの薄膜に
よりほぼ平らになった後に当該材料を硬化する技術を開
発した。The present invention aims to solve the above-mentioned problems in the prior art, and in order to achieve the purpose, the inventor of the present application has created an α-ray shielding material that contains almost no solvent, such as silicone, on a chip. After dropping the material, a thin insulating film is placed on top of the material, and a technique has been developed in which the material is cured after the surface of the axillary material is made almost flat by this thin film.
以下、本発明の方法Ｏ実施例を添付図面を参照して説明
する。Embodiments of the method of the present invention will be described below with reference to the accompanying drawings.
チップ１１０上に、溶媒をほとんど含まないシリコーン
の如きα線遮蔽材料を滴下すると、シリコーンは前記し
丸ように第１図に示す形状をとる。When an α-ray shielding material such as silicone containing almost no solvent is dropped onto the chip 110, the silicone assumes the shape shown in FIG. 1 as the circle described above.
この材料がまだ液状である間に、絶縁性樹脂薄膜１１を
シリコーン材料の上にのせると、シリコーンは第３図に
断面で示す如１形状となる。薄膜１１の膜厚は、シリコ
ーン膜を１００β帛程度に形成するとして、５０μ＋＠
程度にする。テップｌは、通常３〜７−角の大きさに形
成されるので、薄膜の大睡さは、第峨図の平面図におい
て、薄膜の１辺とチップの１辺との間の距離Ｗが２００
μ、、Ｓ度になるように設定する。When the insulating resin thin film 11 is placed on the silicone material while this material is still in liquid form, the silicone assumes the shape shown in cross section in FIG. The thickness of the thin film 11 is 50μ+@, assuming that the silicone film is formed to about 100β film.
to a certain degree. Since the tip l is usually formed to have a size of 3 to 7 degrees, the thickness of the thin film is determined by the distance W between one side of the thin film and one side of the chip in the plan view of Fig. 200
Set it so that it is μ,, S degree.
このような薄膜１１は、前記した厚さの樹脂の陥を、真
空打抜機で上記した寸法に打抜き、薄膜をチップ上のシ
リコーンの上に落とすことによってなされ、かかる作業
は手動的にも自動的にもなしつる。薄膜を落とすには打
抜機の真空をぬくだけでよい。薄膜１１が正確に第４図
に示される位置に落とされることは必要ではなく、薄膜
１１の中心がチップのほぼ中心に近いところにくるよう
に薄膜を落とすと、それはシリコーンの光面張力によっ
て第４図に示す状態をとる。Such a thin film 11 is made by punching out a hole in the resin having the thickness described above to the dimensions described above using a vacuum punching machine, and dropping the thin film onto the silicone on the chip. Such work can be done manually or automatically. Also a vine. To remove the thin film, simply remove the vacuum from the cutting machine. It is not necessary that the thin film 11 be dropped exactly at the position shown in FIG. 4; if the thin film 11 is dropped so that the center of the thin film 11 is approximately close to the center of the chip, it will be moved by the optical surface tension of the silicone. The state shown in Figure 4 is taken.
第３図、第４図に示す如くに薄膜１１がシリコーン上に
浮いた状態で、チップを前記したように恒温槽に入れて
シリコーンを硬化させる。薄膜１１は図示の状態で残る
。それは絶縁性をもつから、配線４に触れてもなんらの
支障も発生しない。With the thin film 11 floating on the silicone as shown in FIGS. 3 and 4, the chip is placed in a constant temperature bath as described above to cure the silicone. The membrane 11 remains as shown. Since it has insulating properties, no trouble will occur even if it touches the wiring 4.
α線対策を強化したいときは、薄膜をα線遮蔽能力のあ
る絶縁性材料で形成する。If you want to strengthen your protection against alpha rays, form the thin film with an insulating material that has the ability to shield alpha rays.
第３図に示される如く表面平らなα線保鰻膜を、ウェハ
上にα線遮蔽材料をスピンコード（回転塗布）によって
平らに塗布し九後に硬化することも考えられたが、スピ
ンコードではシリコーンを１００μｍの膜厚に塗布する
ことはでき々いことが判明した。従りて、シリコーン膜
を前記膜厚で平らに形成するためには、本発明の方法に
よることが最も実際的であることが確認された。As shown in Figure 3, it was also considered to apply an α-ray shielding material flat on the wafer using a spin code (rotary coating) and then harden it after 90 minutes, but with a spin code, It was found that it was not possible to apply silicone to a film thickness of 100 μm. Therefore, it was confirmed that the method of the present invention is the most practical method for forming a flat silicone film with the above-mentioned thickness.
なお、上記の実施例はシリコーンについてのものである
が、本発明の方法はその場合に限定されるものでなく、
その他のα線遮蔽効果をもつ材料が用いられる場合にも
本発明の方法は及ぶ。Note that although the above examples relate to silicone, the method of the present invention is not limited to that case;
The method of the present invention also extends to cases where other materials having an α-ray shielding effect are used.
以上に説明した如く、本発明の方法によると、ＭＯＳメ
モリにおいて、α線に敏感なメモリ素子やセンス増幅器
を含む牛導体チッグ上にα線蓮蔽膜を形成するについて
、その膜を形成する材料が溶媒をほとんど含まぬ液状の
ものであるとき、当該材料をチップ上に滴下し、その材
料がなお液状である間にチップ上にチップより寸法のや
や小な１絶縁性の樹脂材料製薄膜を落とし、液状材料表
圓が平らになった状態で硬化することによシ、α線対策
がとられ、かつ防湿用モールドが形成されたと色このモ
ールドの厚さがほぼ均一になった半導体チップの・譬ツ
ケーゾが形成され、本発明の方法は半導体装置の信頼性
の向上に寄与するものである。As explained above, according to the method of the present invention, in a MOS memory, an α-ray shielding film is formed on a conductor chip including a memory element and a sense amplifier sensitive to α-rays, and the material for forming the film is When the material is in a liquid state containing almost no solvent, the material is dropped onto the chip, and while the material is still in liquid state, a thin film made of an insulating resin material with dimensions slightly smaller than the chip is formed on the chip. When the liquid material is dropped and cured in a flat state, a moisture-proof mold is formed that protects against alpha rays, and the thickness of the mold becomes almost uniform. - The method of the present invention contributes to improving the reliability of semiconductor devices.
第１図は、従来技術による半導体チップ・ヤツケーノの
断面図、第２図は、第１図のチップの平面図、第３図と
第４図は、本発明の方法を実施する工程におけるチップ
を示す断面図と平面図である。
１・・・チップ、２・・・ステーゾ、３・・・リード、
４・・・配線、５・・・モールド樹脂、６・・・α線か
ら保護されるべきチップの領域、７・・・配線電極が形
成されるチップの領域、８・・・シリコーン膜、１１・
・・薄膜。
特許出願人 富士通株式会社
代理人 弁理士 松 岡 宏四部
第１図
］
第２図
゛）３１ 第４１″FIG. 1 is a cross-sectional view of a semiconductor chip according to the prior art, FIG. 2 is a plan view of the chip shown in FIG. 1, and FIGS. FIG. 2 is a cross-sectional view and a plan view. 1...chip, 2...stezo, 3...lead,
4... Wiring, 5... Molding resin, 6... Area of the chip to be protected from alpha rays, 7... Area of the chip where wiring electrodes are formed, 8... Silicone film, 11・
...Thin film. Patent Applicant Fujitsu Limited Agent Patent Attorney Hiroshi Matsuoka Department Figure 1] Figure 2 ゛) 31 No. 41''
Claims (1)
料を滴下し、尚該材料を硬化して皺チッｌ上に保Ｓ＊を
形成する方法にして、蟲腋材料が液状である間に当該材
料上にチップ寸法よりも大でない絶縁性薄膜を配置し、
しかる後に幽諌材料を硬化することを特徴とする半導体
装置の製造方法。A liquid material with almost no solvent is dripped onto the surface of the semiconductor chip, and the material is hardened to form a protective S* on the wrinkled chip, while the underarm material is in a liquid state. placing an insulating thin film no larger than the chip size on the material;
1. A method for manufacturing a semiconductor device, which comprises subsequently curing the ghost material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56098565A JPS58135A (en) | 1981-06-25 | 1981-06-25 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56098565A JPS58135A (en) | 1981-06-25 | 1981-06-25 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58135A true JPS58135A (en) | 1983-01-05 |
| JPS6332267B2 JPS6332267B2 (en) | 1988-06-29 |
Family
ID=14223198
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56098565A Granted JPS58135A (en) | 1981-06-25 | 1981-06-25 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58135A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04197059A (en) * | 1990-11-28 | 1992-07-16 | Toshiba Corp | Cooling structure for electric appliance |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57201033A (en) * | 1981-06-01 | 1982-12-09 | Burroughs Corp | Method of adhering protective film to integrated circuit |
-
1981
- 1981-06-25 JP JP56098565A patent/JPS58135A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57201033A (en) * | 1981-06-01 | 1982-12-09 | Burroughs Corp | Method of adhering protective film to integrated circuit |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04197059A (en) * | 1990-11-28 | 1992-07-16 | Toshiba Corp | Cooling structure for electric appliance |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6332267B2 (en) | 1988-06-29 |
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