JPS61276352A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS61276352A JPS61276352A JP60116767A JP11676785A JPS61276352A JP S61276352 A JPS61276352 A JP S61276352A JP 60116767 A JP60116767 A JP 60116767A JP 11676785 A JP11676785 A JP 11676785A JP S61276352 A JPS61276352 A JP S61276352A
- Authority
- JP
- Japan
- Prior art keywords
- film
- semiconductor device
- conductive film
- semiconductor
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】
(産業上の利用分野)
この発明は、特に静電的な外力を遮蔽して素子の破壊や
素子の特性の劣化を防止できるようにした半導体装置の
製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a method of manufacturing a semiconductor device, which is particularly capable of shielding electrostatic external forces to prevent element destruction and deterioration of element characteristics.
半導体装置における放射線、特にダイナミック型記憶装
置のα粒子によるソフト・エラーを防止する技術に関し
ては、たとえば、特公昭59−48552号公報などで
知られている。Techniques for preventing soft errors caused by radiation in semiconductor devices, particularly alpha particles in dynamic memory devices, are known, for example, from Japanese Patent Publication No. 59-48552.
第3図は従来の半導体装置の製造方法の一例を示す工程
説明図であり、この第3図において、11は半導体基板
、12はy−ト絶縁膜、13はP −計電極、14は拡
散層、15は層間絶縁膜、16は電極取出用配線、17
は絶縁保護膜、18は電極取出用窓を示す。FIG. 3 is a process explanatory diagram showing an example of a conventional method for manufacturing a semiconductor device. In this FIG. layer, 15 is an interlayer insulating film, 16 is wiring for electrode extraction, 17
18 indicates an insulating protective film, and 18 indicates an electrode extraction window.
この従来の製造方法では、まず第3図(a)に示すよう
に、半導体基板11上にP−)絶縁膜12、r−計電極
13、拡散層14、#間絶縁膜15、電極取出用配置j
ll 6t”遂次形成し、半導体素子部を形成する。In this conventional manufacturing method, first, as shown in FIG. Placement
ll 6t" are sequentially formed to form a semiconductor element portion.
しかる後、この半導体素子部を水分や機械的な傷から保
護されるように絶縁保護膜17を形成し、第3図(b)
に示す構成を得る。通常この絶縁保護膜17は気相成長
の酸化膜や高分子樹脂などの絶縁膜から成っている。Thereafter, an insulating protective film 17 is formed to protect the semiconductor element from moisture and mechanical scratches, as shown in FIG. 3(b).
Obtain the configuration shown in Usually, this insulating protective film 17 is made of an oxide film grown in a vapor phase or an insulating film made of polymer resin.
この後、絶縁保護膜17を周知のホトリン技術によシ処
理し、電極取出用窓18を開孔し、第3図(c)のよう
な構造を得て、半導体装置のウニハブ゛ ロセスを終
了する。After this, the insulating protective film 17 is processed by the well-known photorin technology, and the electrode extraction window 18 is opened to obtain the structure shown in FIG. 3(c), thereby completing the uniform processing of the semiconductor device. do.
従来は、この後、α線などの放射線対策として組立工程
時にチップコートと呼は・れるシリコン塗布工程が加え
られていた。Conventionally, after this, a silicon coating process called a chip coat was added during the assembly process as a measure against radiation such as alpha rays.
(発明が解決しようとする問題点)
しかしながら、上記の製造方法では、その後のパツケー
ノング組立工程や半導体装置の取扱い時に誘起される静
電的な外力によシグート絶縁膜が破壊され゛たシ、ある
いはP −)絶縁膜中にエレクトロンなどが注入され、
素子の特性を著しく劣化させるなど、素子の信頼性に問
題があった。(Problems to be Solved by the Invention) However, in the above manufacturing method, the semiconductor insulating film may be destroyed by electrostatic external forces induced during the subsequent package assembly process or handling of the semiconductor device. P-) Electrons etc. are injected into the insulating film,
There were problems with the reliability of the device, such as significant deterioration of device characteristics.
また、α線対策として、チップコートという工程を導入
しなければならない問題があった。Additionally, there was a problem in that a process called chip coating had to be introduced as a countermeasure against alpha rays.
この発明は、前記従来技術が持っている問題点のうち、
静電的な素子の破壊や素子の特性の劣化を招来するとい
う問題点と、チップコートと呼ばれるシリコン塗布工程
を導入しなければならない問題点について解決した半導
体装置の製造方法を提供するものである。This invention solves the problems of the above-mentioned prior art.
The present invention provides a method for manufacturing semiconductor devices that solves the problems of electrostatic destruction of elements and deterioration of element characteristics, and the necessity of introducing a silicon coating process called chip coating. .
(問題点を解決するための手段)
この発明は、半導体装置の製造方法において、半導体素
子上に絶縁保護膜を形成した後に半導体素子を被覆する
ように導電性被膜を形成する工程を導入したものである
。(Means for Solving the Problems) The present invention introduces a step of forming a conductive film to cover the semiconductor element after forming an insulating protective film on the semiconductor element in a method of manufacturing a semiconductor device. It is.
(作 用)
この発明によれば、半導体装置の製造方法に以上のよう
な工程を導入したので、半導体素子上の絶縁保!!l!
膜上の導電性被膜をアース電位の電極に接続すると誘導
された静電気はアースに導く。(Function) According to the present invention, since the above-described steps are introduced into the method of manufacturing a semiconductor device, the insulation on the semiconductor element can be improved. ! l!
When the conductive coating on the membrane is connected to an electrode at ground potential, the induced static electricity is conducted to ground.
(実施例)
以下、この発明の半導体装置の製造方法の一実施例につ
いて図面に基づき説明する。第1図(a)ないし第1図
(c)はその一実施例の工程説明図であシ、第2図はこ
の発明によって得られた半導体装置の平面図である。(Example) An example of the method for manufacturing a semiconductor device of the present invention will be described below with reference to the drawings. FIGS. 1(a) to 1(c) are process explanatory diagrams of one embodiment, and FIG. 2 is a plan view of a semiconductor device obtained by the present invention.
この第1図(a)〜第1図(c)および第2図において
、21は半導体基板、22はP−)、18緑膜、23は
P−ト電極、24は拡散層、25は層間絶縁膜、26は
電極取出用配線、27は絶縁保護膜、28は電極取出用
窓、29は導電性被膜、30は導電性被膜開口窓、31
は半導体素子のアース電位と導電性被膜の電気的接続部
、32はアース電位の電極を示す。1(a) to 1(c) and FIG. 2, 21 is a semiconductor substrate, 22 is a P-), 18 is a green film, 23 is a P-to electrode, 24 is a diffusion layer, and 25 is an interlayer. Insulating film, 26 is wiring for electrode extraction, 27 is an insulating protective film, 28 is a window for electrode extraction, 29 is a conductive film, 30 is a conductive film opening window, 31
3 represents an electrical connection between the ground potential of the semiconductor element and the conductive film, and 32 represents an electrode at the ground potential.
まず、第1図(&)は半導体素子上に形成された絶縁保
護膜27に電極取出用窓28を形成し、従来のウェハプ
ロセスを完了した半導体装置の構成を示すものである。First, FIG. 1 (&) shows the configuration of a semiconductor device in which an electrode extraction window 28 is formed in an insulating protective film 27 formed on a semiconductor element, and a conventional wafer process is completed.
この発明では、この後第1図(b)に示すごとく、導電
性被膜29を半導体装置全面に被着する。導電性被膜2
9はAl 、 Ti 、 W 、 Moなどの金属でよ
いが異種金属間の電池効果による腐食を避けるため電極
取出用配線と同種の金属がよい。この導電性被膜29の
被着の方法は、蒸着法、スパッタ法、CVD法、塗布法
などいずれでもよいが被着時の物理的影響(ダメージな
ど)を素子に与えないCVD法、塗布法が好ましい。In the present invention, a conductive film 29 is then deposited on the entire surface of the semiconductor device as shown in FIG. 1(b). Conductive film 2
9 may be a metal such as Al, Ti, W, Mo, etc., but it is preferable to use the same type of metal as the electrode lead wiring to avoid corrosion due to the battery effect between different metals. The conductive film 29 may be deposited by any method such as vapor deposition, sputtering, CVD, or coating, but CVD and coating methods that do not cause physical effects (damage, etc.) on the device during deposition are preferred. preferable.
また、導電性被膜29の被着時の温度は半導体素子の変
成を避けるよう550°以下で行う。導電性被膜29の
膜厚は特に制限はないが、絶縁保護膜27のステップで
段切れが起こらない程度の膜厚であればよい。Further, the temperature at which the conductive film 29 is deposited is 550° or less to avoid metamorphosis of the semiconductor element. The thickness of the conductive film 29 is not particularly limited, but may be a thickness that does not cause breakage in the steps of the insulating protective film 27.
このようにして、導電性被膜29を半導体装置の全面に
被着した後、周知のホ) IJソ技術によシ第1図(c
)に示すように導電性被膜29の開口窓30を形成する
。このとき導電性被膜29は第2図に示すようにアース
電位の電極32と一部が重なるようにして、第1図(c
)および第2図に示すような半導体素子のアース電位と
導電性被膜29の電気的接続部3工を形成する。After the conductive film 29 is deposited on the entire surface of the semiconductor device in this way, it is coated with the well-known IJ method as shown in FIG.
), an opening window 30 of the conductive film 29 is formed. At this time, the conductive coating 29 is partially overlapped with the electrode 32 at the ground potential as shown in FIG.
) and three electrical connections between the ground potential of the semiconductor element and the conductive film 29 as shown in FIG.
導電性被膜29はアース電位の電極32の全領域を覆っ
た状態では、後の組立工程のポンディグ性が他の電極と
異なるので、これを防ぐためにも導電性被膜開口窓30
が必要である0
このときのホトリソ工程では、アース電位の電極32以
外の電極は導電性被膜29全通しての短絡を防ぐため、
この電極部32およびその周囲数ミクpンの領域の導電
性被膜29も同時にエツチング除去する。When the conductive film 29 covers the entire area of the electrode 32 at ground potential, the ponging property in the subsequent assembly process will be different from that of other electrodes, so in order to prevent this, the conductive film opening window 30 is
In the photolithography process at this time, the electrodes other than the electrode 32 at earth potential are
This electrode portion 32 and the conductive coating 29 in an area several micrometers around it are also etched away at the same time.
このようにして、半導体素子上に導電性被膜29を形成
し、この導電性被膜29と半導体素子内のアース電位電
極とを接続した構造の半導体装置を得る。In this way, a semiconductor device having a structure in which the conductive film 29 is formed on the semiconductor element and the conductive film 29 is connected to the earth potential electrode within the semiconductor element is obtained.
さらに、この導電性被膜の接地は、半導体装置外部の端
子から引き込んでもよく、この場合、前記半導体装置形
成後にこの導電性被膜と外部接地端子とを接続する工程
を加えればよい。Further, the conductive film may be grounded from a terminal outside the semiconductor device, and in this case, a step of connecting the conductive film and the external ground terminal may be added after the semiconductor device is formed.
(発明の効果)
以上詳細に説明したように、この発明によれば、半導体
素子を覆うように導電性被膜を絶縁保護膜を介して設け
、これを素子のアース電位に接続するようにしたので、
パツケーソング組立工程や半導体装置の取扱い時に誘起
される静電的な外力を遮蔽することができる。(Effects of the Invention) As explained in detail above, according to the present invention, a conductive film is provided via an insulating protective film to cover a semiconductor element, and this is connected to the earth potential of the element. ,
It is possible to shield electrostatic external forces induced during the packaging process or during the handling of semiconductor devices.
したがって、それによる半導体素子の破壊や、素子特性
の劣化を防止でき、素子の信頼性を向上できる利点があ
る。Therefore, it is possible to prevent destruction of the semiconductor element and deterioration of the element characteristics due to this, and there is an advantage that the reliability of the element can be improved.
%K、5OI(シリコンオンインシュレータ)構造を有
するデバイスにおいては、外部の静電的な影響を受けや
すく、この発明を適用することにより、この問題は解決
される。さらに、外部からのα線などの放射線も導電性
被膜によシ遮蔽することができるので、従来行っていた
チップコート工程を省、略できる利点がある。さらK、
°この発明はMO8半導体装置全例にして説明してきた
が、他の半導体装置に応用しても静電的な遮蔽や耐放射
線性を期待できることは言うまでもない。A device having a %K, 5OI (silicon-on-insulator) structure is susceptible to external electrostatic influences, and this problem can be solved by applying the present invention. Furthermore, since external radiation such as alpha rays can be shielded by the conductive coating, there is an advantage that the conventional chip coating process can be omitted. Sara K,
Although this invention has been explained using all MO8 semiconductor devices as an example, it goes without saying that electrostatic shielding and radiation resistance can be expected when applied to other semiconductor devices.
第1図(a)ないし第1図(c)はこの発明の半導体装
置の製造方法の一実施例の工程説明図、第2図は同上半
導体装置の製造方法で得られた半導体装置の平面図、第
3図(a)ないし第3図(c)は従来の半導体装置の製
造方法の工程説明図である。
21−0.半導体基板、22・・・ダート絶縁膜、23
・・・P−)電極、24・・・拡散層、25・・・層間
絶縁膜、26・・・電極取出用配線、27・・・絶縁保
護膜、28・・・電極取出用窓、29・・・導電性被膜
、30・・・導電性被膜開口窓、31・・・電気的接続
部、32・・・アース電位の電極。
特許出願人 沖電気工業株式会社
半導体装x/)手面図
第2因
第3図1(a) to 1(c) are process explanatory diagrams of an embodiment of the method for manufacturing a semiconductor device of the present invention, and FIG. 2 is a plan view of a semiconductor device obtained by the method for manufacturing the semiconductor device described above. , FIG. 3(a) to FIG. 3(c) are process explanatory diagrams of a conventional method for manufacturing a semiconductor device. 21-0. Semiconductor substrate, 22... dirt insulating film, 23
... P-) Electrode, 24... Diffusion layer, 25... Interlayer insulating film, 26... Wiring for electrode extraction, 27... Insulating protective film, 28... Window for electrode extraction, 29 . . . conductive film, 30 . . . conductive film opening window, 31 . . . electrical connection portion, 32 . Patent applicant: Oki Electric Industry Co., Ltd. Semiconductor Equipment
Claims (2)
と、 (b)上記半導体素子上に絶縁保護膜を被着し電極部に
対応する開口部を形成する工程と、 (c)上記絶縁保護膜を介して上記半導体素子上に導電
性被膜を被着する工程と、 (d)半導体装置の接地電極に対応する上記開口部を除
く他の開口部上の上記導電性被膜を除去する工程と、 よりなることを特徴とする半導体装置の製造方法。(1) (a) a step of forming a semiconductor element on a semiconductor substrate; (b) a step of depositing an insulating protective film on the semiconductor element and forming an opening corresponding to an electrode portion; (c) the above-mentioned step. (d) removing the conductive film on other openings other than the opening corresponding to the ground electrode of the semiconductor device; A method for manufacturing a semiconductor device, comprising the steps of:
開口部よりこの導電性被膜を除去する工程と、(b)残
存する導電性被膜と半導体装置の外部接地端子を接続す
る工程と、 を有することを特徴とする特許請求の範囲第1項記載の
半導体装置の製造方法。(2) (a) Step of removing the conductive film from the opening corresponding to the electrode part after depositing the conductive film, and (b) connecting the remaining conductive film to the external ground terminal of the semiconductor device. The method for manufacturing a semiconductor device according to claim 1, comprising the steps of:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60116767A JPS61276352A (en) | 1985-05-31 | 1985-05-31 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60116767A JPS61276352A (en) | 1985-05-31 | 1985-05-31 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS61276352A true JPS61276352A (en) | 1986-12-06 |
Family
ID=14695225
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP60116767A Pending JPS61276352A (en) | 1985-05-31 | 1985-05-31 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61276352A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02201954A (en) * | 1989-01-30 | 1990-08-10 | Nec Corp | Manufacture of semiconductor storage device |
US6570203B2 (en) | 2000-09-18 | 2003-05-27 | Fujitsu Limited | Semiconductor device and method of manufacturing the same |
JP2010258396A (en) * | 2008-06-16 | 2010-11-11 | Fuji Electric Systems Co Ltd | Mos semiconductor device |
-
1985
- 1985-05-31 JP JP60116767A patent/JPS61276352A/en active Pending
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02201954A (en) * | 1989-01-30 | 1990-08-10 | Nec Corp | Manufacture of semiconductor storage device |
US6570203B2 (en) | 2000-09-18 | 2003-05-27 | Fujitsu Limited | Semiconductor device and method of manufacturing the same |
EP1189262A3 (en) * | 2000-09-18 | 2003-11-12 | Fujitsu Limited | Semiconductor device comprising a capacitor and method of manufacturing the same |
US6706540B2 (en) | 2000-09-18 | 2004-03-16 | Fujitsu Limited | Method of manufacturing a semiconductor device with a hydrogen barrier layer |
JP2010258396A (en) * | 2008-06-16 | 2010-11-11 | Fuji Electric Systems Co Ltd | Mos semiconductor device |
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