JPS5858645A - Converting system of decimal number and binary number - Google Patents

Abstract

PURPOSE:To increase a speed of converting operation, by checking whether the byte concerned is all zero or not at every 1 byte from the upper rank part of a converting data, and omitting the converting operation by the number of zero connected in the upper rank part of the converting data. CONSTITUTION:In case of a CVB instruction, as for an operation of B'j=B'j-1X 10+dj, 4 operation cycles consisting of shifting operation of 2 times and adding operation of 2 times are required, but as for a speed for skipping the operation, it can be executed by about 1.5 operation cycles by deciding whether the upper rank byte is zero or not. Accordingly, the operation cycle of a converting data of 40 bits becomes as follows: 1.5 operation cycles + converting operation 10 times, when 1 byte ''0'' is not ''0''. 3 Operation cycles + converting operation 8 times, when byte ''1'' is ''0''. 4.5 Operation cycles + converting operation 6 times, when byte 2 is ''0''. 6 Operations cycles + converting operation 4 times, when byte 3 is ''0''. 7.5 Operation cycles + converting operation 2 times, when byte 4 is ''0''. In this way, except the case when byte ''0'' is not ''0'', the operating speed is increased.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for converting decimal numbers and binary numbers using a microprogram-controlled computer, which can omit conversion operations and improve conversion speed.

Conventionally, in the conversion method between decimal and binary numbers using micro-program controlled computers, there are six commands: CVB instruction for converting from decimal number to binary number, and CVD instruction for converting from binary number to lθ base number. The conversion algorithm is as follows.

Mori, CVB instruction algorithm D-(d@dld,・・・・・・・・・ 4) Dou・;
Decimal number before conversion.

B= (6・h168・・・・・・・・・～)s;
Multiplying by 1 and adding with the converted binary number are performed in binary format for each 4 bits.

B・'w d・ 8';~X10+dl B,/Ten Bt'X 10 + d@ ■ B/= B j-/X 10 + dlB = B,/
X 10 + d.

However, B/ is an intermediate result〇mi, CVD instruction algorithm B:l+=(&h1&3... b%)
3; Take the binary number before conversion, and groove it by 3 bits from the high order: B z (0eOxOr......F) $
becomes. Then, assume that the converted lO-adic number is D-to (dId1d-to) to, and the multiplication and addition are performed in lO-adic increments of 4 bits.

)′=to DXI〒I), X8+Oi D4 export 5-1'x s + o i ! : D% wealth Dn-t’X　to 8+ However, ■ indicates interim results.

Finally, in the case of a CVD instruction, the conversion operation is repeated for all digits of the converted data as shown in Figure 1 (0). When 6 is all zero, s B? Even if the calculation 1'×io+d7 is executed, the result will be 0, resulting in wasted noise during calculation time.

In view of the foregoing, the present invention provides means for checking whether each byte from the upper part of the converted data can contain all zeros in a method for converting decimal numbers and binary numbers using a micro-program controlled computer; And by providing a means for jumping to the conversion operation procedure for the byte among the conversion operation procedures for IO base and binary numbers for each byte from the upper part of the conversion data when a byte that is not all zero is found. Embodiments of the present invention will be described below with reference to the accompanying drawings, the object of which is to provide a system for converting decimal numbers and binary numbers by omitting conversion operations by the number of consecutive zeros in the upper part.

Figure 2 shows that the data to be converted and the converted data are stored in a circuit used for converting decimal numbers and binary numbers, and the logic operation unit (ALU5) is a binary number. The shifter 5FT6 has the function of performing addition and decimal addition, and the shifter 5FT6 shifts data left and right.0 Moves data to each register The movement is controlled by the microphone in the control storage C87; the microphone in the control storage C87;
The program is addressed by address register C81R9 and finally read out to C register 8. C register 8
The code read out becomes a microinstruction and controls the movement of each data.

Considering the calculation speed in CVD instructions, nj"-mj
The operation of -1'X10+dj takes 4 operation cycles, 2 shift operations and 2 addition operations, but the speed of skipping the operation by checking whether the upper byte becomes zero or not is about 1.5
It can be executed in arithmetic cycles. Therefore, according to the flowchart shown in Fig. 3, the conversion data is loaded onto the
The control storage C8711f includes an instruction to jump to the μ-byte conversion operation procedure from the base number conversion operation procedure.

Therefore, as shown in FIG. 4, the calculation cycle for 40-bit conversion data is: (1) When byte 0 is not 0, 1.5 calculation cycles + 10 conversion calculations.

■When byte 1 is 0, 3 operation cycles + 8 conversion operations.

■When byte 2 is 0, 4.5 operation cycles + 6 conversion operations.

■When byte 3 is 0, 6 operation cycles + 4 conversion operations.

■When byte 4 is 0, it becomes 7.5 calculation cycles + 2 conversion calculations, and the calculation speed improves except for cases where byte 0 is not 0.

In addition, instead of simply ticking or ticking from the high-order byte of the conversion data, we check the frequency of the used pattern and detect it from the case of 2 significant figures for Pol's Sebut-Isidex instruction. You can also do this.

Also, in the case of CVD instructions, one operation D, /-1)7
−; Since the conversion operation can be omitted by the number of zeros, the speed of the conversion operation between decimal numbers and binary numbers can be improved.

[Brief explanation of drawings]

Figure 1 shows an example of conversion data used in the present invention.
FIG. 2 shows a circuit used in the present invention, FIG. 3 is a flowchart showing an embodiment of the present invention, and FIG. 4 shows an example of shortening the calculation cycle according to an embodiment of the present invention.・4-Cal Storage, 5...Er. x:”
Knit, 6... Shifter, 7... Control Storage. Patent Applicant: Fujitsu Ltd. Representative Patent Attorney Kyotani 4 Sections --The next 1st and 2nd time.

Claims (1)

[Claims] In the method of converting lθ base numbers and binary numbers using a micro program control computer, 1 from the upper part of the converted data
Kl for each byte
By providing the step Rt for jumping to the conversion operation step 11 for the armpit byte in the conversion operation procedure of the base number, it is possible to omit the conversion operation by the number of zeros that are continuous in the upper part of the conversion data. .