JPS592055B2 - Square root calculation method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a square root calculation method, and particularly to a square root calculation method that utilizes the characteristics of binary numbers.

Conventionally, when performing square root calculation on an electronic computer,
Using the four arithmetic instructions, such as Newton's method,
Approximate values are usually obtained using software.

On the other hand, desktop calculators use a method in which the square root is determined by adding up the number of permutations of odd numbers to the open whole number. In the case of this conventional method,
There was a risk that the configuration would become complicated and that various errors would occur during calculations. In view of the above points, the present invention aims to provide a square root calculation method that can obtain square roots with high precision and high speed with a simple configuration.

Embodiments of the square root calculation method according to the present invention will be described below with reference to the drawings. FIG. 1 shows an example of f-b square root calculation obtained by hand calculation using binary numbers.

This calculation method is similar to the square root operation in decimal and is well-known, but in decimal, it is necessary to try 10 different numbers from 0 to 9 and perform division to find the remainder. In comparison, in the case of binary, there are only two types of numerical values, ``O'' and ``1'' as shown in Figure 1, so all arithmetic operations can be performed only by digit shifting and addition/subtraction.
In addition, the numerical values indicated by symbols A, B, C, and D in FIG. 1 correspond to the register contents A, B, C, and D shown in FIG. 2, respectively.
It corresponds to

If we convert the *flat root found in this figure to decimal, we get the following formula, which matches the decimal value. FIG. 2 shows an arithmetic device that executes the arithmetic operations shown in FIG.

This device has a register A in which the undivided fraction indicated by the symbol A in FIG. It has a register C and a register D in which the square root indicated by the symbol D is set.

Furthermore, a subtractor SU that takes the difference between the contents of registers B and C
A comparator C that compares B and the contents of registers B and C.
MP and an adder AD that adds 1 to the contents of register C
D and a counter C that counts the required number of digits n of the heir force root to be found.
NT and a step control STC for instructing calculation steps. Next, the operation of the arithmetic unit shown in FIG. 2 will be explained with reference to FIGS. 3 and 5.

FIG. 3 is a flowchart showing the operation of the arithmetic device of FIG. Furthermore, Fig. 5 shows the changes in the contents A, B, C, and D of each register when the arithmetic unit shown in Fig. 2 is used to square root a binary number 10 using the square root calculation power formula shown in Fig. 1. It is an explanatory diagram showing each step. In addition, step 1
2, 3, 3', 4, 5 are steps 1, 2, 3,
3', 4, and 5. First, register A is set to 10, and registers B, C, and D are reset (set to 0). Next, calculation step 1 is executed. That is, the most significant digit of register A and the least significant digit of register B are connected, these registers are shifted two digits (two bits) to the left, and O is shifted into the least significant digit of register A. In this case, in the example of FIG. 5, register A becomes 00 and register B becomes 10. Next, step 2
Do this.

In step 2, 1 is added to register C by adder ADD (in the example of FIG. 5, C=0+1-1), and this is compared with the contents of register B by comparator CMP. If the result of this comparison is B - C, the process proceeds to step 3; if B<C, the process proceeds to step 3'. In the example of FIG. 5, B = 10,
Since C=1 and B is C, proceed to step 3. Step 3
, the contents of register C are subtracted from the contents of register B by subtractor SUB (B-(B)-(C)), and the result of the subtraction is set in register B again.

If this is done, B=10-1-1 in the example of FIG. At the same time, adder ADD adds 1 to register C (C-(0+1)) and increases the contents of register D by 1 (D=(1))+1). That is, the least significant bit of register D is set to 1. In this way, C=1+1=10, D=0+121.
If B<C, step 3 is executed (fifth step).
In the illustrated example, the program does not proceed to step 3' at first.) In step 3', the contents of register C are decremented by 1.

That is, it is sufficient to set the least significant bit to 0. The operation of adding 1 to register C and comparing it with register B in steps 2, 3, and 3' corresponds to 0 to 9 in decimal notation.
You have to try different types of numerical values, but if you perform operations using binary numbers, you can get "O" and "1" as shown in the example in Figure 5.
There can only be two kinds of numbers, and if "1" is not possible, it is "O", and the answer of the digit being tried can only be "O" or "1", so the remainder is B itself (B - C rice 0) or (
It is a simple logic that B-C rice 1). Step 3 above (if B<C, step 3')
After the processing up to this point has been completed, the end of the calculation is determined in step 4.

This is to count how many times the above operation has been repeated by the counter CNT, and to determine whether or not the number of digits of the square root is less than the required number of square root digits. If the required number of digits has not been reached, the process moves to step 5. In this step 5, register C
, D are shifted one bit to the left, and "O" is shifted into the least significant digit of C and D. In this way, in the example of FIG. 5, register C becomes 10-100, and register D becomes 10-100.
becomes Bokutoge 10. Thereafter, the process returns to step 1, and as shown in the example of FIG. 5, the above calculation is repeated until the required number n of power root digits is obtained.

When the count value of the counter CNT reaches n, the process moves to step 6, and the calculation ends. The value of register D at this time becomes the square root value expressed in binary. In this way, since the calculation process in the above embodiment is only digit shift (bit shift) and addition/subtraction, various errors do not occur during the process, and the calculation process is high precision, high speed, inexpensive, and simple. You can get roots.

In particular, when applied to electronic computers, it is very effective as it only requires a few additional changes to the existing hardware and firmware. The square root number can be given as a double word, and the root can be a single word. Note that in the configuration shown in Figure 2,
Although a subtracter SUB and a comparator CMP are provided, only SUBl subtracters can be provided and these can also serve as a comparator.

This allows the number of circuit elements to be reduced. Also, when the required number of digits for the square root to be found is n, register C is (n
+1) If the bit length is set, register D can be omitted. In other words, the contents of register C at the end of the operation are D.
Since it is twice C, 1 = σ, so 2
Then, VA is obtained by shifting the contents of register C to the right by 1 bit or by n bits by connecting the most significant digit and the least significant digit of the register.

Electronic computers usually have a 1-bit register for carrying up and down in addition and subtraction, so you can use that. In the explanation of the above embodiment, we took as an example the case where calculations after the required digit are discontinued (values after that are rounded down), but instead of simply rounding down, it is also possible to round off after calculating one more digit You can also do it. In this way, execute the rounder and register D
The operation in the case where is omitted is shown in the flowchart of FIG. In this case, register A! '1tn rice 2 bits, B is n
The bit register C is an (n+1) bit register, N is a repeat number counter, and n is the repeat number. Steps 1 to 5 are substantially the same as in the case of FIG. 3, except that step 6A1 and step 7 are newly added. In step 6A, the contents of register C are divided by 2 to find the square root, and in step 7, the least significant digit is rounded off.
In other words, if we assume that one more digit is to be calculated after completing n calculations, what is always shifted into register B from register A in step 1 is a two-digit ``0'' (already in n calculations). (This is because the original contents of A have all been shifted into B.) Also, the least significant digit of register C is always "
O", and when "O" or "1" is set below it, the value to be set in D is determined depending on how it compares with B, but the last two digits of B are "00". Therefore, the last two digits of B and the last digit of C are rounded down and compared, (8)>(C)
It is equivalent to rounding up if (B)≦(C), and rounding down if (B)≦(C). Therefore, in step 7, the contents of B and C are compared and rounded up or rounded down. Note that even if the number to be handled is a floating point number, square rooting can be performed as follows.

Floating point numbers are represented by an exponent and a mantissa.

The square root is the index divided by 2 and the number of f pages. If the exponent is an even number, it can be found in the same way by finding the square root of the number according to the above embodiment. If the exponent is an odd number, the exponent may be made smaller or larger by one digit to make it an even number, corrected by shifting the mantissa, and then the square root of the mantissa is taken to make the exponent equal to one. To divide the exponent part by 2, it is enough to shift it one bit to the right, and the bits overflowing from the lowest digit of the register storing the exponent part are either "1" (odd number) or "0".
” (an even number), it may be determined whether or not to correct the mantissa part. The amount of correction for the mantissa is that the mantissa has binary digits,
When specified in octal digits or hexadecimal digits, digits may be shifted by 1 bit, 3 bits, or 4 bits, respectively. As described above, according to the method of this invention, square roots can be obtained with high precision and high speed with a simple configuration.

[Brief explanation of the drawing]

Fig. 1 is an explanatory diagram showing the case where square root is executed by hand calculation using binary numbers, Fig. 2 is a block diagram showing an embodiment of the square root calculation method according to the present invention, and Fig. 3 is a flowchart showing its operation. , FIG. 4 is a flowchart showing another embodiment,
Figure 5 shows the register contents A when the square root of a binary number 10 is calculated using the calculation method shown in Figure 1 using the calculation device shown in Figure 2.
, B, C, and D. A, B, C, D... Lujista, ADD...
・Adder, CMP... Comparator, CNT...
...Counter, SUB...Subtractor.

Claims (1)

[Claims] 1. A first method for shifting the contents A of the first register, in which the arrangable fraction is set, into the second register two digits at a time starting from the most significant digit.
a second step of comparing the content B of the second register with the content C of the third register whose least significant digit is set to 1; 2 and set (C+1) to the third register.
and a third step of setting the content C in the third register by 1 when B<C, and when the first to third steps are not repeated a predetermined number of times. , after shifting the content C of the third register to the upper digit by one digit and setting 0 to the lowest digit,
The first to third steps are repeatedly executed, and when the first to third steps are repeated a predetermined number of times, an operation result twice the square root result is generated in the third register. A square root calculation method characterized by the following. 2 The third step is a step of subtracting the content C of the third register by 1 and setting the content D of the fourth register to 1 when B<C, and the first to third steps are If it is not repeated the number of times, shift the contents C and D of the third and fourth registers to the upper digits by one digit and set 0 to the lowest digit of each, and then Claim 1, wherein the third step is repeatedly executed, and when the first to third steps are repeated a predetermined number of times, a square root result is generated in the fourth register. Square root calculation method.