JPS5856463A - Light energizing semiconductor device - Google Patents
Light energizing semiconductor deviceInfo
- Publication number
- JPS5856463A JPS5856463A JP15517981A JP15517981A JPS5856463A JP S5856463 A JPS5856463 A JP S5856463A JP 15517981 A JP15517981 A JP 15517981A JP 15517981 A JP15517981 A JP 15517981A JP S5856463 A JPS5856463 A JP S5856463A
- Authority
- JP
- Japan
- Prior art keywords
- region
- emitter region
- auxiliary
- layer
- emitter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 27
- 239000012535 impurity Substances 0.000 claims abstract 2
- 239000004020 conductor Substances 0.000 claims description 13
- 230000035945 sensitivity Effects 0.000 abstract description 6
- 238000009792 diffusion process Methods 0.000 abstract description 3
- 230000003321 amplification Effects 0.000 description 4
- 238000003199 nucleic acid amplification method Methods 0.000 description 4
- 230000003287 optical effect Effects 0.000 description 4
- 230000007423 decrease Effects 0.000 description 3
- 238000010304 firing Methods 0.000 description 2
- NBJBFKVCPBJQMR-APKOLTMOSA-N nff 1 Chemical compound C([C@H](NC(=O)[C@H](CCC(N)=O)NC(=O)[C@H](CCC(N)=O)NC(=O)[C@@H]1CCCN1C(=O)[C@H](CCCCN)NC(=O)[C@@H]1CCCN1C(=O)CC=1C2=CC=C(C=C2OC(=O)C=1)OC)C(=O)N[C@@H](CC=1C=CC=CC=1)C(=O)NCC(=O)N[C@@H](CC(C)C)C(=O)N[C@@H](CCCCNC=1C(=CC(=CC=1)[N+]([O-])=O)[N+]([O-])=O)C(=O)NCC(O)=O)C1=CC=CC=C1 NBJBFKVCPBJQMR-APKOLTMOSA-N 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 244000309464 bull Species 0.000 description 1
- 230000000994 depressogenic effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 239000000835 fiber Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
- H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
- H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
- H01L31/111—Devices sensitive to infrared, visible or ultraviolet radiation characterised by at least three potential barriers, e.g. photothyristors
- H01L31/1113—Devices sensitive to infrared, visible or ultraviolet radiation characterised by at least three potential barriers, e.g. photothyristors the device being a photothyristor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/083—Anode or cathode regions of thyristors or gated bipolar-mode devices
- H01L29/0839—Cathode regions of thyristors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electromagnetism (AREA)
- Ceramic Engineering (AREA)
- Thyristors (AREA)
Abstract
Description
【発明の詳細な説明】 本発明は、光付勢半導体装置の改良Ｃ：関する。[Detailed description of the invention] The present invention relates to improvement C of a photoactivated semiconductor device.
一般（二党付勢牛導体装置、特に光村勢チイリスタは、
主回路と制御（ロ）路の間の電気絶縁性、耐ノイズ性が
優れているため、高電圧パルストランスや＾圧部ゲー）
ｆｇＩｊｆ！ｉなどの多くの制御圓ｊ１３部品を不景ζ
二して装置の小ｍ＠童化が可能となり・装置全体の信頼
性を高めることができる・而して、光付努サイリスタの
トリが光源としては、一般にはＧａＡｓ 系発光ダイ
オードが使用されている０元ファイバと発光ダイオード
の組み合わせで得られるこの光エネルギーは、電気トリ
かエネルギーの数十分の−と非常に小さい。General (two-party power conductor device, especially Mitsumura power conductor device,
It has excellent electrical insulation and noise resistance between the main circuit and the control (b) path, so it is suitable for high voltage pulse transformers and voltage section games).
fgIjf! Many control circle j13 parts such as i are depressed ζ
Second, the device can be made smaller and the reliability of the entire device can be improved.As a light source, GaAs-based light emitting diodes are generally used as the light source for the light-emitting thyristor. The light energy obtained by the combination of the zero-element fiber and the light emitting diode is extremely small, several tenths of the energy of an electric tree.
このため、光付勢サイリスタの光トリガ感度は、電気ト
リガサイリスタのトリガ感度より数十倍高的る必要があ
る。しかしながら、光トリが感度を高めると、急峻な立
上りの電圧（二よる誤点弧、所謂ｄｖ／ｄｔ 耐量が
低下する０受光部＠Ｊ棟を小さくすればｄ ｖ／ｄ を
耐量は改善されるが、初期点弧領域が減少し、ｄｉ／ｄ
ｔ耐量が低下する。Therefore, the optical trigger sensitivity of the optically activated thyristor needs to be several tens of times higher than the trigger sensitivity of the electrically triggered thyristor. However, when the sensitivity of the photodetector increases, the voltage with a sharp rise (false firing due to double ignition, so-called dv/dt) withstand capacity decreases.If the 0 light receiving part @J building is made smaller, the withstand capacity of dv/d can be improved. However, the initial firing area decreases and di/d
t tolerance decreases.
このため、光付努チイリスタには増幅ゲート構造や多段
増幅ゲート構造が採用され℃いる。こＣＤ場合、ｄｉ／
ｄｔ＃量は改讐されるが、サイリスタが点弧するため（
＝必要な最小の陽極電圧であるフィンガー電圧（ＶＦＩ
Ｎ ）が増加する。フィンガー電圧が高いとサイリスタ
の並列運転時に、先にターンオンしたサイリスタにのみ
電流か流れ、他のサイリスタは永久にターンオンしなく
なってしまう問題があった。For this reason, an amplification gate structure or a multi-stage amplification gate structure is adopted in the optical transistor. In the case of this CD, di/
The dt# amount is revised, but since the thyristor fires (
= the minimum required anode voltage, the finger voltage (VFI
N ) increases. If the finger voltage is high, there is a problem that when thyristors are operated in parallel, current flows only to the thyristor that is turned on first, and the other thyristors are not turned on forever.
本発明は、かかる点：二鑑みてなされたもので、光トリ
ガ感度、ｄｖ／ｄｔ耐量、ｄ ｉ ／ｄ を耐量が＾く
、しかもフィンガー電圧の低い光付勢牛導体装置を提供
するものである・
以下、本発明の実施例について図面を参照して説明する
。The present invention has been made in view of these two points, and provides an optically energized conductor device that has high optical trigger sensitivity, dv/dt tolerance, and di/d tolerance, and has low finger voltage. Embodiments of the present invention will be described below with reference to the drawings.
第１図は・本発明の一実施例の断面図である。FIG. 1 is a sectional view of one embodiment of the present invention.
図中１は、Ｐ型半導体層からなるＰエミツタ層である。1 in the figure is a P emitter layer made of a P-type semiconductor layer.
Ｐエミツタ層１上Ｃ：は、Ｎｆｉ牛導体層からなるＮベ
ース層２が形成されている。Ｎペース層２上には、Ｐｆ
ｊ１牛導体層からなるＰベース層３が形成されている。On the P emitter layer 1, an N base layer 2 made of an Nfi conductor layer is formed. On the N pace layer 2, Pf
A P base layer 3 made of a conductor layer is formed.
Ｐベース層３の中央部には、Ｎ型半導体層（二分離部４
１を形成してなる略Ｃ字型の第１補助エミツタ領域４が
所定の拡散深さで形成されている。また、Ｐベース層３
（−は、第１補助エミクタ領域４を囲むようζ二して同
様イニ分離部５ａを有するＮ！１半導体層からなる略Ｃ
字型の第２補助エミクタ領域５が形成されている。Ｐベ
ース層３の周辺部Ｃ：は。In the center of the P base layer 3, there is an N-type semiconductor layer (bi-separation part 4).
A substantially C-shaped first auxiliary emitter region 4 is formed with a predetermined diffusion depth. In addition, P base layer 3
(- is an abbreviation C consisting of an N!1 semiconductor layer that surrounds the first auxiliary emitter region 4 and has a similar ini isolation portion 5a.
A letter-shaped second auxiliary emitter region 5 is formed. Peripheral portion C of P base layer 3: Ha.
Ｎ型半導体層からなる主エミツタ領域６が第２補助エミ
ツタ領域５を囲むよう（二形成されている◎主エミッタ
領域６には、多数のエミッタ短絡孔７ａ（二連じる孔１
ｂを有する主陰極８が形成されている。＃Ｉｌ補助エミ
ンタ領域４及び第２補助エミクタ領域５上（＝は、Ｐベ
ース層３（＝跨がるように紀１補助電極９、第２補助電
極１０が夫々形成されている。また、Ｐエミッタ層１の
下面砿：は陽極１１が形成されている。A main emitter region 6 made of an N-type semiconductor layer is formed so as to surround the second auxiliary emitter region 5. The main emitter region 6 has a large number of emitter shorting holes 7a (two consecutive holes 1
A main cathode 8 having a diameter b is formed. #A first auxiliary electrode 9 and a second auxiliary electrode 10 are formed on the Il auxiliary emitter region 4 and the second auxiliary emitter region 5 (= means the P base layer 3 (== the first auxiliary electrode 9 and the second auxiliary electrode 10 are formed over the P An anode 11 is formed on the lower surface of the emitter layer 1 .
このよう（二構成された光付勢牛導体装置１２（：よれ
ば、第１補助エミクタ領域４で囲まれた受光部ＩＳＯ面
積を小さくしてｄｖ／ｄｔ １ｔｉｉを高め、かつ、第
２補助エミツタ領域５を設けた増幅ゲート構造区二よっ
てｄｉ／ｄｔ耐蓋を高めることができる・しかも、動作
時の電流（Ｉ）は、Ｐエミツタ層１とＮペース層２間の
ＰＮ＠合＾、へペース層２とＰベース層３間のＰＮ接合
（ハ）、第１補助電極９．Ｐベース層３を経てＰベース
層３と王エミッタ領域６間のＰＮ＠合一に至る４つのＰ
Ｎ接合（５）・・・鋤を通過して流れる。従って。According to the light energizing conductor device 12 (2) configured in this way, the ISO area of the light receiving part surrounded by the first auxiliary emitter region 4 is reduced to increase dv/dt 1tii, and the second auxiliary emitter region 4 is The di/dt resistance can be increased by the amplification gate structure section 2 provided with the region 5.Moreover, the current (I) during operation is reduced to the PN junction between the P emitter layer 1 and the N space layer 2. PN junction (c) between the space layer 2 and the P base layer 3, the first auxiliary electrode 9. The four Ps that pass through the P base layer 3 and reach the PN@union between the P base layer 3 and the main emitter region 6
N junction (5)...Flows through the plow. Therefore.
補助エミッタ領域と王エミッタ領域が左右対称形をなす
従来の構造のもの（：比べて、電流（Ｉ）の通過するＰ
Ｎ接合の数が少なくなり（従来の場合では５つ）、フィ
ンガー電圧（ｖｙｎｔ ）を小さくすることができる。Compared to the conventional structure in which the auxiliary emitter region and the main emitter region are left-right symmetrical (: P through which the current (I) passes)
The number of N junctions is reduced (5 in the conventional case), and the finger voltage (vynt) can be reduced.
尚、実施例の他（−も第２１（：示す如く、第２補助エ
ミクタ領域５を分離部５ａを有する略Ｃ字形のＮｆｆ１
半導体層で形成し、受光部１３′をＮ型の半導体層１４
で形成した光付勢牛導体装置１５Ｃ：も適用することは
勿論である。同図中、実施例のも゛のと同一部分は、同
一符号を付している。In addition, in addition to the embodiment (- is also the 21st (: As shown, the second auxiliary emitter region 5 is a substantially C-shaped Nff1 having a separating part 5a.
The light receiving section 13' is formed of a semiconductor layer 14 of an N type.
It goes without saying that the optically energized conductor device 15C formed by the above method can also be applied. In the figure, the same parts as those in the embodiment are given the same reference numerals.
次に、上記光付勢牛導体装置１２，１５を特定発明とし
、その主要部を構成（：有する本願の第２の発明１：つ
いて第３図を参照して説明する。Next, the light-energized bull conductor devices 12 and 15 are defined as a specific invention, and the second invention 1 of the present application, which has the main parts thereof, will be explained with reference to FIG. 3.
図中２０は、Ｐｆｉ半導体層からなるＰエミッタ層であ
る。 Ｐエミッタ層２ｏ上Ｃ：は、Ｎ型半導体層からな
るＮベース層２１を介してＰ型半導体層からなるＰベー
ス層２２が形成されている。Ｐベース層２２の中央部Ｃ
二は、所定の拡散深さのＮ呈牛導体層からなる第１補助
エミツタ領域２３とこれを所定間隔を設けて囲むように
形成され、かつ一部分でＮＭｌ半導体層２３１Ａで接続
された＃！２禎助エミッタ領域２４が形成されている。In the figure, 20 is a P emitter layer made of a Pfi semiconductor layer. On the P emitter layer 2o, a P base layer 22 made of a P type semiconductor layer is formed via an N base layer 21 made of an N type semiconductor layer. Center part C of P base layer 22
#2 is formed to surround the first auxiliary emitter region 23 made of an N-type conductor layer with a predetermined diffusion depth at a predetermined interval, and is partially connected to the NMI semiconductor layer 231A. Two Teisuke emitter regions 24 are formed.
Ｐベース層２２０周辺部には、第２補助エミツタ領域２
４を囲むよう４ニジてＮｆｉ半導体層からなる主エミツ
タ領域２５が形成されている。主エミツタ領域２５は、
Ｎｆｆ１半導体層ＪＪｂを介して＃Ｉ２Ｉ２補助エダク
タ領域２４１＆続されている。A second auxiliary emitter region 2 is provided around the P base layer 220.
A main emitter region 25 made of an Nfi semiconductor layer is formed at four sides so as to surround the main emitter region 4 . The main emitter region 25 is
The #I2I2 auxiliary eductor region 241 & is connected via the Nff1 semiconductor layer JJb.
主エミツタ領域２５上には、多数のエミッタ短絡孔２６
１（二連じる孔２６ｂを有する主陰極２１が形成されて
いる。第１補助エミッタ領域２３、第２補助エミッタ領
域２４上ｉ：は、Ｐイー２層２２（：跨がるよう（＝し
て第１補助電極２８、第２補助電極２９が夫々形成され
ている。Ｐエミツタ層２０の下面には、陽極３０が形成
されている。A large number of emitter shorting holes 26 are provided on the main emitter region 25.
1 (a main cathode 21 having two consecutive holes 26b is formed). A first auxiliary electrode 28 and a second auxiliary electrode 29 are respectively formed thereon.An anode 30 is formed on the lower surface of the P emitter layer 20.
このように構成された光付勢牛導体装置３１（＝よれば
、第１補助エミクタ領域２３で凹まれた受光部３２０面
槓を小さくしてｄｙ／ｄｔ １ｔｉｉを高め、かつ、第
２補助エミクタ領域２４を設けた増幅ゲート構造によっ
てｄｉ／ｄｔ耐童を高耐量ことができる。しかも、動作
時の電流（２）は、Ｐエミツタ層２０・Ｎベース層２１
間のＰＮ接合（ト））、Ｎベース層２１とＰベース層２
２間のＰＮ接合（）１、及びＰベース＄２２と第１補助
エミッタ層２３間のＰＮ接合００３つのＰＮ接合（８・
・・（ｑを通過して流れる。従って、補助エミッタ領域
と主エミツタ領域が左右対称形をなす従来の構造のもの
（ニルべて、電流の通過するＰＮ接合の数が少なくなり
（従来の場合では５つ）、フィンガー電圧（ＶＦＩＮ
）を小さくすることができる。According to the light-energizing conductor device 31 (=) configured in this way, the light-receiving portion 320 surface recessed in the first auxiliary emitter region 23 is made smaller to increase dy/dt 1tii, and the second auxiliary emitter The amplification gate structure provided with the region 24 can achieve high di/dt resistance.Moreover, the current (2) during operation is
PN junction (g) between N base layer 21 and P base layer 2
2 PN junctions ()1, and PN junctions between the P base $22 and the first auxiliary emitter layer 003 PN junctions (8.
...(current flows through 5), finger voltage (VFIN
) can be made smaller.
尚、前記実施例の他Ｃ：も第４図に示す如く、受光部３
２′をＰイー２層２２に通じるＰ型子導体層で形成した
光付努半導体装置３３にも適用できることは勿論である
。同図中前記実施例のものと同一部分は、同一符号を付
している。In addition to the above embodiment, C: also has a light receiving section 3 as shown in FIG.
Of course, the present invention can also be applied to a light-emitting semiconductor device 33 in which 2' is formed of a P-type conductor layer communicating with the P-E2 layer 22. In the figure, the same parts as those in the previous embodiment are designated by the same reference numerals.
また、第５図に示す如く、前記第３図及び第４図に示す
光付勢半導体装置３２．ＪＪの他Ｃ二も第５図に示す如
く、主エミツタ領域２５と第２補助エミクタ領域２４間
だけを両者と同じＮ型子導体層３４で接続するようＣ二
した光付勢半導体装置３５にも適用できることは勿論で
ある〇同図中、第４図（−示す光付勢半導体装置３３と
同一部分については、同一符号を付している０以上説明
した如く、本発明に係る光付勢半導体装置によれば、光
トリガ感度、ｄｖ／ｄｔ耐量、ｄｔ／ｄｔ耐量を高くし
て、しかもフィンガー電圧を低くすることができる等顕
著な効果を有するものである。Further, as shown in FIG. 5, the photo-energized semiconductor device 32 shown in FIGS. 3 and 4 above. As shown in FIG. 5, in addition to JJ, C2 is also used in a photo-energized semiconductor device 35 in which only the main emitter region 25 and the second auxiliary emitter region 24 are connected by the same N-type conductor layer 34 as both. Of course, the same parts as the optically activated semiconductor device 33 shown in FIG. The semiconductor device has remarkable effects such as being able to increase optical trigger sensitivity, dv/dt tolerance, and dt/dt tolerance, and lower finger voltage.
第１図は、本発明の一実施例の断面図、第２図は、他の
実施例の断面図、纂３図は、第１図及び第２図（−示す
特定発明の光付勢半導体装置の主要部を構成（＝有する
本願の第２の発明の一実施例の断面図、第４図及びＩＰ
Ｊ５図は、第３図（＝示す光付勢半導体装置の他の実施
例の断面図である。
１．２０・・・Ｐエミッタ層、２．２１・・・Ｎペース
層、３，２２・・・Ｐベース層、４．２３・・・第１補
助エミンタ領域、５．２４・・・第２補助エミクタ領域
、６．２６・・・主エミツタ領域、１ａ。
２６Ｂ・・・エミッタ短絡孔、７ｂ、２６ｂ・・・孔、
８．２１・・・主陰極、９．２８・・・第１１ｉ助電極
、１０．２５１・・・第２補助電極、１１．３０・・・
陽極、出願人代理人 弁理士 鈴 江 武 彦ｊＩＩ
図
程
１
第２図
担FIG. 1 is a cross-sectional view of one embodiment of the present invention, FIG. 2 is a cross-sectional view of another embodiment, and FIG. A cross-sectional view of an embodiment of the second invention of the present application comprising the main part of the device, FIG.
Figure J5 is a sectional view of another embodiment of the optically energized semiconductor device shown in Figure 3. 1.20...P emitter layer, 2.21...N paste layer, 3,22... ... P base layer, 4.23... First auxiliary emitter region, 5.24... Second auxiliary emitter region, 6.26... Main emitter region, 1a. 26B... Emitter shorting hole, 7b, 26b...hole,
8.21...Main cathode, 9.28...11i-th auxiliary electrode, 10.251...2nd auxiliary electrode, 11.30...
Anode, applicant's representative Patent attorney Suzue Takehiko jII
Plan 1 2nd figure
Claims (2)
に異なる導電型の半導体層の４層を順次積層し、該半導
体層の最上層が補助エミッタ領域とこれを囲む王エミク
タ領域とからなり、該補助エミッタ領域の所定領域１：
分ｌＩＩ部を形成したことを特徴とする光付勢半導体装
置。(1) Between adjacent layers (to form two PN junctions = four layers of semiconductor layers of mutually different conductivity types are sequentially stacked, and the top layer of the semiconductor layer forms an auxiliary emitter region and a king emitter region surrounding it). Predetermined region 1 of the auxiliary emitter region:
A photo-energized semiconductor device characterized in that a part II portion is formed.
互を二異なる導′ｆｌＬ型の半導体層の４鳩を順次積層
し、該半導体層の最上層が補助エミッタ領域とこれを囲
む王エミクタ領域とからなり、該補助エミッタ領域の所
定領域と前記玉エミクタ領域の所定領域とを同一導電型
の不純物領域で一体く＝接続せしめたことを特徴とする
光付勢牛導体装置。(2) Between adjacent layers (to form two P-N junctions:
Four semiconductor layers of the type FILL with two different conductivity are sequentially stacked, and the uppermost layer of the semiconductor layer consists of an auxiliary emitter region and a king emitter region surrounding it, and a predetermined region of the auxiliary emitter region and the ball A light-energized conductor device characterized in that a predetermined region of an emitter region is integrally connected to an impurity region of the same conductivity type.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15517981A JPS5856463A (en) | 1981-09-30 | 1981-09-30 | Light energizing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15517981A JPS5856463A (en) | 1981-09-30 | 1981-09-30 | Light energizing semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5856463A true JPS5856463A (en) | 1983-04-04 |
Family
ID=15600211
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15517981A Pending JPS5856463A (en) | 1981-09-30 | 1981-09-30 | Light energizing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5856463A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6064469A (en) * | 1983-09-19 | 1985-04-13 | Hitachi Ltd | Photo thyristor |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5021347A (en) * | 1973-06-27 | 1975-03-06 | ||
| JPS50120279A (en) * | 1974-02-18 | 1975-09-20 | ||
| JPS5183784A (en) * | 1974-12-10 | 1976-07-22 | Siemens Ag | |
| JPS51139278A (en) * | 1975-05-28 | 1976-12-01 | Hitachi Ltd | Semi_conductor controlled rectifier device |
| JPS5352377A (en) * | 1976-10-25 | 1978-05-12 | Hitachi Ltd | Thyristor |
| JPS549871A (en) * | 1977-06-25 | 1979-01-25 | Kawasaki Heavy Ind Ltd | Device of intermittently transferring and placing soft body to be carried |
-
1981
- 1981-09-30 JP JP15517981A patent/JPS5856463A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5021347A (en) * | 1973-06-27 | 1975-03-06 | ||
| JPS50120279A (en) * | 1974-02-18 | 1975-09-20 | ||
| JPS5183784A (en) * | 1974-12-10 | 1976-07-22 | Siemens Ag | |
| JPS51139278A (en) * | 1975-05-28 | 1976-12-01 | Hitachi Ltd | Semi_conductor controlled rectifier device |
| JPS5352377A (en) * | 1976-10-25 | 1978-05-12 | Hitachi Ltd | Thyristor |
| JPS549871A (en) * | 1977-06-25 | 1979-01-25 | Kawasaki Heavy Ind Ltd | Device of intermittently transferring and placing soft body to be carried |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6064469A (en) * | 1983-09-19 | 1985-04-13 | Hitachi Ltd | Photo thyristor |
| JPH029460B2 (en) * | 1983-09-19 | 1990-03-02 | Hitachi Ltd |
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