JPS5856444U - Transistor with two terminal circuit - Google Patents
Transistor with two terminal circuitInfo
- Publication number
- JPS5856444U JPS5856444U JP14967981U JP14967981U JPS5856444U JP S5856444 U JPS5856444 U JP S5856444U JP 14967981 U JP14967981 U JP 14967981U JP 14967981 U JP14967981 U JP 14967981U JP S5856444 U JPS5856444 U JP S5856444U
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- terminal circuit
- circuit
- terminal
- printed conductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Amplifiers (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図a、 bはエミッタ接地形およびベース接地形
のC扱高周波電力増幅器の入力回路図、第2図a〜dは
第1図においてトランジスタを0級にバイアスする二端
子回路の各種回路図、第3図a。
bは第1図a、 bの回路における実装構造図、第4
図a、 bは本考案の実施例の平面図および側面
′図、第5図a、 bは本考案の第2の実施例の
平面−図および側面図、第66図は本考案の具体的構成
を説明する斜視図である。図において、
1・・・・・・トランジスタ、2・・・・・・入力端子
、3・・・・・・二端子回路、4・・・・・・コイルま
たは線路、5・・・・・・抵抗体、6・・・・・・接地
端子、7・・・・・・リード(エミッタまたはベース)
、訃・・・・・コレクタ、9・・・・・・キャップ、1
0・・・・・・接地底板、11・・・・・・パターン、
12゜13・・・・・・接続点、14・・・・・・内面
、である。Figures 1a and 1b are input circuit diagrams of C-handling high-frequency power amplifiers with grounded emitter and grounded base configurations, and Figures 2a to d are various circuit diagrams of two-terminal circuits that bias the transistors to class 0 in Figure 1. , Figure 3a. b is a mounting structure diagram of the circuits in Figs. 1a and b; Fig. 4
Figures a and b are a plan view and side view of an embodiment of the present invention.
1, 5a and 5b are a plan view and a side view of the second embodiment of the present invention, and FIG. 66 is a perspective view illustrating the specific structure of the present invention. In the figure, 1...transistor, 2...input terminal, 3...two-terminal circuit, 4...coil or line, 5...・Resistor, 6...Ground terminal, 7...Lead (emitter or base)
, Death...Collector, 9...Cap, 1
0...Ground bottom plate, 11...Pattern,
12゜13...connection point, 14...inner surface.
Claims (1)
は印刷導体と抵抗素子との回路からなる二端子回路を形
成し、この二端子回路の両端をトランジスタのベースと
エミッタとの間に接続することを特徴とする二端子回路
つきトランジスタ。A two-terminal circuit consisting of a printed conductor circuit or a circuit of a printed conductor and a resistance element is formed on the insulating package of the transistor, and both ends of this two-terminal circuit are connected between the base and emitter of the transistor. Transistor with two terminal circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14967981U JPS5856444U (en) | 1981-10-08 | 1981-10-08 | Transistor with two terminal circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14967981U JPS5856444U (en) | 1981-10-08 | 1981-10-08 | Transistor with two terminal circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5856444U true JPS5856444U (en) | 1983-04-16 |
Family
ID=29942440
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP14967981U Pending JPS5856444U (en) | 1981-10-08 | 1981-10-08 | Transistor with two terminal circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5856444U (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5619911B2 (en) * | 1975-02-06 | 1981-05-11 |
-
1981
- 1981-10-08 JP JP14967981U patent/JPS5856444U/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5619911B2 (en) * | 1975-02-06 | 1981-05-11 |
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