JPS5856152A - プログラム変換装置 - Google Patents

プログラム変換装置

Info

Publication number
JPS5856152A
JPS5856152A JP56155016A JP15501681A JPS5856152A JP S5856152 A JPS5856152 A JP S5856152A JP 56155016 A JP56155016 A JP 56155016A JP 15501681 A JP15501681 A JP 15501681A JP S5856152 A JPS5856152 A JP S5856152A
Authority
JP
Japan
Prior art keywords
sentence
redefinition
loop
variable
parallel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56155016A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6229816B2 (enExample
Inventor
Yukio Kamiya
幸男 神谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56155016A priority Critical patent/JPS5856152A/ja
Publication of JPS5856152A publication Critical patent/JPS5856152A/ja
Publication of JPS6229816B2 publication Critical patent/JPS6229816B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Devices For Executing Special Programs (AREA)
JP56155016A 1981-09-30 1981-09-30 プログラム変換装置 Granted JPS5856152A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56155016A JPS5856152A (ja) 1981-09-30 1981-09-30 プログラム変換装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56155016A JPS5856152A (ja) 1981-09-30 1981-09-30 プログラム変換装置

Publications (2)

Publication Number Publication Date
JPS5856152A true JPS5856152A (ja) 1983-04-02
JPS6229816B2 JPS6229816B2 (enExample) 1987-06-29

Family

ID=15596830

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56155016A Granted JPS5856152A (ja) 1981-09-30 1981-09-30 プログラム変換装置

Country Status (1)

Country Link
JP (1) JPS5856152A (enExample)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62202235A (ja) * 1986-03-03 1987-09-05 Hitachi Ltd コンパイラにおけるル−プ展開方式
JPS63304325A (ja) * 1987-06-05 1988-12-12 Hitachi Ltd 並列化コンパイル方法
JPH02126322A (ja) * 1988-11-07 1990-05-15 Nec Corp 情報処理装置

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62202235A (ja) * 1986-03-03 1987-09-05 Hitachi Ltd コンパイラにおけるル−プ展開方式
JPS63304325A (ja) * 1987-06-05 1988-12-12 Hitachi Ltd 並列化コンパイル方法
JPH02126322A (ja) * 1988-11-07 1990-05-15 Nec Corp 情報処理装置

Also Published As

Publication number Publication date
JPS6229816B2 (enExample) 1987-06-29

Similar Documents

Publication Publication Date Title
US6308316B1 (en) Apparatus for analyzing operations of parallel processing system
ATE113399T1 (de) Verfahren und gerät zur fehlererkennung und - korrektur in einem nach dem überlappten steuerungsverfahren arbeitenden rechnersystem.
JPH0776921B2 (ja) データ処理方法及び装置
JPH0628178A (ja) 算術演算を簡略にする最適化装置及び方法
JPS5856152A (ja) プログラム変換装置
JP2557629B2 (ja) 割込方式
JPH05334465A (ja) 演算器・記憶装置・データ転送装置必要数計数装置
JPS63157241A (ja) 関数型処理装置
JPH01142951A (ja) パイプライン演算器
KR200323622Y1 (ko) 인터럽트 중재 로직
US20070168788A1 (en) Detector in parallel with a logic component
Makhaniok et al. Synchronization of parallel processes in distributed systems
JPS6297031A (ja) 仮数部のビツト数整合方式
JPH0236423A (ja) 退避／復帰レジスタアドレス生成回路
JPH0644270B2 (ja) ベクトルプロセッサの制御処理方式
JPH0342731A (ja) 検証手段付き処理装置
JPH0340143A (ja) パイプライン方式計算機におけるデバッグ方式
Murray Some Observations on Equivalence Handling Methods
JPH04286031A (ja) プログラムのループ並列実行処理方法
JPH0675927A (ja) マルチプロセッサシステム
JPH04120630A (ja) 実行命令数の計数方法及び装置
JPS62160529A (ja) デ−タ処理装置
JPH01223565A (ja) 情報処理装置
JPH02309423A (ja) パイプラインプロセッサにおける実効アドレス計算制御方式
JPH02126322A (ja) 情報処理装置