JPS5856152A - Program converting device - Google Patents

Program converting device

Info

Publication number
JPS5856152A
JPS5856152A JP56155016A JP15501681A JPS5856152A JP S5856152 A JPS5856152 A JP S5856152A JP 56155016 A JP56155016 A JP 56155016A JP 15501681 A JP15501681 A JP 15501681A JP S5856152 A JPS5856152 A JP S5856152A
Authority
JP
Japan
Prior art keywords
sentence
redefinition
loop
variable
parallel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56155016A
Other languages
Japanese (ja)
Other versions
JPS6229816B2 (en
Inventor
Yukio Kamiya
幸男 神谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56155016A priority Critical patent/JPS5856152A/en
Publication of JPS5856152A publication Critical patent/JPS5856152A/en
Publication of JPS6229816B2 publication Critical patent/JPS6229816B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Devices For Executing Special Programs (AREA)

Abstract

PURPOSE:To effectively utilize the performance of a computer system which have plural arithmetic units capable of performing parallel operation by converting instructions of a developed program, etc., which can not be executed in parallel into instructions which can be executed in parallel. CONSTITUTION:A prescribed number of sentences of a program to be converted are inputted to an input buffer 1 at every time. Once a D0 sentence detecting means 2 detects a D0 sentence, the sentence and a succeeding execution sentence are transferred to a working register 4. Then, a redefinition detecting means 5 detects whether a variable is redefined or not. When not, a selector 6 is controlled to output the sentence to an output buffer 10. When the variable is redefined, the index value of a step for the redefinition is calculated by an index value detecting means 7 and on the basis of the value, a D0 loop deviding means 8 generates plural D0 loops newly and outputs them to the output buffer 10.

Description

【発明の詳細な説明】 本発明はプログラム変換装置に関し、特に並列に動作で
きる複数の演算処理装置金具えて高スループッIf狙う
計算機に使用して効果?あげるために、できるだけ並列
処理可能な部分を多く含むようにプログラムを変換する
ものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a program conversion device, and is particularly effective when used in a computer that is equipped with a plurality of arithmetic processing units that can operate in parallel and aims for high throughput. In order to increase this, the program is converted to include as many parts that can be processed in parallel as possible.

例えば下記のようなりoループは一般によく現われる〇 Dolo ニー為 N DOIOJ劇1.N ム(J)−ム(J)十B (J)*ム(1)10  0
ONT工NUN このようなプログラム変換装置の演算器會有する計算機
で実行するとき、内側のDOループにおいてもし変数A
 (1) t一定数とみなせれば、2台の演算器でJ−
1〜NまでのNステップの半分づつ全分担させて並列処
理させることができる。しかし上記の例ではJが工と等
しくなったとき、A(1)の値が変化(再定義)してし
まう。つまvJが工より大きい範囲と、Jが工より小さ
い範囲とでにA (1)の値が異なる。従って2台の演
算器に単純に分担させることができず、従来ではこのよ
うなループは直列に処理していかざるを得なかった。
For example, o-loops as shown below commonly appear. N Mu (J) - Mu (J) 10 B (J) * Mu (1) 10 0
ONT Engineering When executing on a computer with such a program conversion device arithmetic unit, if the variable A in the inner DO loop is
(1) If t can be regarded as a constant number, J-
Parallel processing can be performed by fully sharing half of the N steps from 1 to N. However, in the above example, when J becomes equal to engineering, the value of A(1) changes (redefines). The value of A (1) differs between the range where vJ is larger than ku and the range where J is smaller than ku. Therefore, it is not possible to simply divide the work between two arithmetic units, and in the past, such loops had to be processed in series.

本発明はこのような従来の問題点を解決すること金目的
としており、以下図面により説明する0図は本発明の一
実施例ブロック図であり、簡単のために本発明に直接関
係する部分のみ示しであるが、これにさらにコンパイラ
機能等を追加してもよい。
The purpose of the present invention is to solve such conventional problems, and Figure 0, which will be explained below with reference to the drawings, is a block diagram of one embodiment of the present invention, and for the sake of simplicity, only the parts directly related to the present invention will be shown. Although this is shown, further compiler functions etc. may be added to this.

図において被変換プログラムは所定数のセンテンスづつ
入力バッフアユに入力される。人力センテンスの命令文
の中からDO文検出手段2によりDO文の有無全検出す
る。DO文が無ければセレクタ3を制御してORゲート
9を介してそのit出出力バッファlへ出力する。
In the figure, the program to be converted is input to the input buffer in units of a predetermined number of sentences. The DO sentence detection means 2 detects the presence or absence of all DO sentences from among the command sentences of human sentences. If there is no DO statement, the selector 3 is controlled and the output is sent to the it output buffer l via the OR gate 9.

DO文が検出されるとそのセンテンス及びそれに続く実
行文(等式など)をワークレジスタ番に移す。セして^
定義検出手段5によって変数の再定義の有無が検出され
る。再定義の有無は、例えば前記の例では等号(−)の
両辺に同一変数名が有るか否か、有った場合にそのイ/
デクスが異なるにもかかわらすイ/デクス値が同一にな
る可能性があるか否を調べればよい。
When a DO statement is detected, that sentence and the following executable statement (such as an equation) are moved to the work register number. Set it ^
The definition detection means 5 detects whether or not a variable has been redefined. The presence or absence of redefinition can be determined by, for example, whether or not the same variable name exists on both sides of the equal sign (-) in the above example, and if so, whether the variable name is the same or not.
It is sufficient to check whether there is a possibility that the i/dex values are the same even though the indexes are different.

同、ここで「f数名」とは上記例におけるAOlBに)
であり、「インデクス」とは工、Jであり「インデクス
値Jとは工、JK具体的数値を代入したものをいう。ま
た単に「変数」というときは具体的インデクス値で特定
された変数名の値をいうO また再定義が生じ得るとしてもその再定義後の変数が再
び同−DOループで使用されなければ問題はないので、
その場合は再定義とみなさない。
Same, here "f number" refers to AOLB in the above example)
, the "index" is , J, and the "index value J is the value obtained by substituting a specific numerical value. Also, when we simply say "variable", we mean the variable name specified by the specific index value. Also, even if redefinition may occur, there is no problem as long as the variable after the redefinition is not used again in the same -DO loop, so
In that case, it will not be considered a redefinition.

このようにしてもし再定義がなければ、セレクタ6を制
御して出力バッファ10へ出力する。
In this way, if there is no redefinition, the selector 6 is controlled to output to the output buffer 10.

再定義を生じている場合には、インデクス値検出手段ツ
によりその再定義會生じるステップのインデクス値を算
出し、その値にもとづいてDOルーズ分割手段8によっ
て、複数のDOループを新たに生成し、出力バッファ1
0に出力する。即ち上記の例ではJ−1〜工までのDo
ループとJ−工+1−M1でのDOループに分割し、元
のり。
When a redefinition occurs, the index value detection means calculates the index value of the step that causes the redefinition, and based on that value, the DO loose division means 8 generates a plurality of new DO loops. , output buffer 1
Output to 0. That is, in the above example, Do from J-1 to Engineering
Divide into a loop and a DO loop with J-work + 1-M1, and paste the original.

ループと置換える。以下にその結果の例を示す。Replace with loop. An example of the results is shown below.

DOIOI−1,N DO20J−λ 工 A(J) −A(J)十B(、T)* A(1)20 
   C0NT工NUI DOIOJ−工+1.N A(J) −A(J)+ B(J)* A(1)10 
  C0NT工NUI このようにすれば最初のDOループ(DO20)におい
ては再定義は無いので、複数台の演算器で分担して並列
処理ができる。2番目のDoループ(DOlo)におい
ても同様である。但し、D。
DOIOI-1,N DO20J-λ Engineering A (J) -A (J) 10 B (, T) * A (1) 20
C0NT Engineering NUI DOIOJ- Engineering +1. N A(J) −A(J)+ B(J)* A(1)10
C0NT Engineering NUI In this way, there is no redefinition in the first DO loop (DO20), so multiple computing units can share the task and perform parallel processing. The same applies to the second Do loop (DOlo). However, D.

20とDo 10とを並列処理することはできない。20 and Do10 cannot be processed in parallel.

D020が終らねばDoloにおける変数A(1)が定
まらないからである。
This is because the variable A(1) in Dolo cannot be determined until D020 is completed.

また再定義される変数が2以上存在する場合には、DO
ループの分割数も3以上とすればよい。
Also, if there are two or more variables to be redefined, DO
The number of loop divisions may also be three or more.

以上の如く本発明によれば、既開発のプログラム等にお
ける並列実行不可能な命令を並列実行可能なものに変換
し、並列動作可能な複数の演算器を有する計算機システ
ムの能力を有効に利用することが可能となる。
As described above, according to the present invention, instructions that cannot be executed in parallel in an already developed program are converted into instructions that can be executed in parallel, and the ability of a computer system having multiple arithmetic units that can operate in parallel is effectively utilized. becomes possible.

【図面の簡単な説明】[Brief explanation of drawings]

図は本発明の一実施例ブロック図であり、1は入力バッ
ファ、2はDO文検出手段、5は再定義検出手段、7は
インデクス値検出手段、8はDOループ分割手段、10
は出力バッファである。 代理人 弁理士 松 岡 宏四部
The figure is a block diagram of an embodiment of the present invention, in which 1 is an input buffer, 2 is a DO statement detection means, 5 is a redefinition detection means, 7 is an index value detection means, 8 is a DO loop division means, 10
is the output buffer. Agent Patent Attorney Hiroshi Matsuoka

Claims (1)

【特許請求の範囲】[Claims] 入力プログラム中にDOループの有無全検出する手段と
、腋DOループの中における変数の再定義の有無を検出
する手段と、該再定義を生じるインデクス値を求める手
段と、上記DOループを上記インデクス値までのDOル
ープと、上記インデクス値の次の値から始まるDOルー
プとに分割する手段とを臭えたこと1−%像とするプロ
グラム変換装置〇
means for detecting the presence or absence of a DO loop in an input program; means for detecting the presence or absence of a redefinition of a variable in the armpit DO loop; means for determining an index value that causes the redefinition; A program conversion device that uses a 1-% image of a means for dividing a DO loop up to a value and a DO loop starting from the next value of the index value.
JP56155016A 1981-09-30 1981-09-30 Program converting device Granted JPS5856152A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56155016A JPS5856152A (en) 1981-09-30 1981-09-30 Program converting device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56155016A JPS5856152A (en) 1981-09-30 1981-09-30 Program converting device

Publications (2)

Publication Number Publication Date
JPS5856152A true JPS5856152A (en) 1983-04-02
JPS6229816B2 JPS6229816B2 (en) 1987-06-29

Family

ID=15596830

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56155016A Granted JPS5856152A (en) 1981-09-30 1981-09-30 Program converting device

Country Status (1)

Country Link
JP (1) JPS5856152A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62202235A (en) * 1986-03-03 1987-09-05 Hitachi Ltd Loop developing system for compiler
JPS63304325A (en) * 1987-06-05 1988-12-12 Hitachi Ltd Parallel compiling system
JPH02126322A (en) * 1988-11-07 1990-05-15 Nec Corp Information processor

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62202235A (en) * 1986-03-03 1987-09-05 Hitachi Ltd Loop developing system for compiler
JPS63304325A (en) * 1987-06-05 1988-12-12 Hitachi Ltd Parallel compiling system
JPH02126322A (en) * 1988-11-07 1990-05-15 Nec Corp Information processor

Also Published As

Publication number Publication date
JPS6229816B2 (en) 1987-06-29

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