JPH02309423A - Effective address calculation control system in pipeline processor - Google Patents

Abstract

PURPOSE:To rapidly execute effective address calculation and to prevent the execution cycle time of a pipeline stage from being prolonged by executing effective address calculation shorter than the whole address length in respective divided modules in parallel. CONSTITUTION:The subject system is constituted of divided effective address calculation modules 1, input registers 11, 12, an effective address adder 13, an effective address register 15, etc. For instance, effective address calculation is divided into upper and lower modules, the effective address is calculated by respective divided modules 1 in parallel, and when a carry is detected in the calculation process or the carry is predicted, a pipeline is interlocked. The carry is added to the calculated result of the upper side and the added result is connected to the interlocked lower side calculation result to form a real effective address. Consequently, the effective address calculation can rapidly be executed and the execution cycle time of the pipeline stage can be prevented from being prolonged.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Application Fields Conventional Technology and Problems to be Solved by the Invention Means for Solving the Problems Actions Examples Effects of the Invention (Overview) Operates in a pipeline system Regarding the effective address calculation method in processors, the aim is to perform effective address calculations at high speed and to prevent the execution cycle time of pipeline stages from becoming long. For example, divide the divided module into two modules, calculate the effective address independently in each divided module, and detect the presence or absence of a carry from the module sharing the lower address, or The carry is predicted using the upper few bits of the lower module, and if there is no carry, the normal pipeline operation continues, the calculation results of each module are combined, and the carry from the lower module is predicted. is detected or a carry is predicted, the pipeline is interlocked, the carry is added to the calculation result in the upper module, and then the result and the interlock are added. The lower calculation results are combined to form an effective address.

[Field of Industrial Application] The present invention relates to an effective address calculation method in a processor operating in a pipelined manner.

Traditionally, one way to improve the processing power of computer systems is to divide the processing executed by one instruction into multiple stages and construct a pipeline in which the processing mechanisms at each stage are connected in series. , each time an instruction comes in,
There is a pipeline method in which a plurality of instructions are processed in parallel on a stage-by-stage basis by inputting instructions into the pipeline.

When processing data on a computer using the pipeline method, it is necessary to shorten the execution cycle at each stage as much as possible. The applications of processors are becoming more and more diverse, and there are various demands such as faster processing, expansion of address space, and increase in processing word length, and it is difficult to efficiently process these demands. It's becoming necessary.

For example, as mentioned above, due to the expansion of the address space, there is a problem that the execution time in the effective address calculation stage of the pipeline becomes longer, and this has become a factor that hinders the increase in the execution speed of the pipeline. There is now a need for an effective address calculation control method that can shorten the execution time required for effective address calculation.

[Prior art and problems to be solved by the invention] Fig. 3 is a diagram explaining an effective address calculation control method in a conventional pipeline processor. , (a2) shows a configuration example when the address length is 2X bits, (bl),
(b2) shows an operation time chart in each case.

Conventionally, an effective address calculation unit in a processor that operates in a pipeline system processes all address bits (for example, X bits or 2X bits), as shown in this figure.
are added in one calculation cycle.

That is, the effective address calculation stage of the pipeline shown in FIGS. (bl) and (b2) is designed to have a sufficient cycle time including the carry propagation time from the lower bits.

Therefore, it is necessary to set the pipeline cycle time to take into account the carry propagation time from the lower bits of the address to be added, and if the effective address calculation stage is the time bottleneck among all pipeline stages. In this case, the address length is increased (for example, in this figure (al
) Figure → (a2) Figure) The effective address calculation time becomes longer (see (bl) figure → (b2) figure), which causes a problem that reduces the performance of processors that operate in a pipeline system. .

In order to speed up the carry propagation, a carry look ahead technique is known, but the propagation time still increases in proportion to the address length.

In view of the above-mentioned conventional drawbacks, the present invention provides an effective address calculation control method that can perform effective address calculation at high speed and prevent the execution cycle time of the pipeline stage from increasing in a processor that operates in a pipeline system. The purpose is to

[Means to solve the problem]

FIG. 1 is a diagram explaining the present invention in detail.

The above problem is solved by an effective address calculation control method in a pipeline processor configured as follows.

(1) In a processor that operates in a pipeline system, the effective address calculation module is divided into multiple modules with multiple bits of the effective address as a unit, and each divided module calculates the effective address independently. , detect the presence or absence of a carry from each module sharing the lower address, and if there is no carry, continue normal pipeline operation, combine the calculation results of each module, and calculate the corresponding digit. If there is a carry, interlock the pipeline and add the carry to the calculation result in each upper module until there is no carry in each module, and then add the result and the carry. The calculation results of each interlocked lower order are combined to form an effective address.

(2) In a processor that operates in a pipeline system, the effective address calculation module is divided into multiple modules with multiple bits of the effective address as a unit, and each divided module calculates the effective address independently. , predict a carry using the upper few bits of each module that shares the lower address, and if it is predicted that there will be no carry, continue normal pipeline operation and calculate the calculation results of each module. When the carry is predicted to occur, the pipeline is interlocked and the carry is added to the calculation result in each upper module until there is no carry in each module. After repeating, the result is combined with the interlocked lower-order calculation results to form an effective address.

[Effect]

That is, according to the present invention, an effective address calculation module of a processor that operates in a pipelined manner -
The effective address bits are divided into n divisions, for example, into two, and the effective address is calculated independently in each divided module. Or, ■Use a look-ahead carry circuit made up of the upper few bits of the divided lower address to predict a carry from the lower bit, and if there is no carry from the lower bit, , the normal pipeline operation is performed and the calculation results of the upper address/lower address are combined to form the effective address, but if a carry from the lower address is detected, or if a carry is predicted to occur. To do this, interlock the pipeline with the detection signal or prediction signal, add a carry to the effective address calculation result on the upper side, and then combine that result with the interlocked calculation result on the lower side. are combined to form the effective address.

When implementing the present invention, if there is a carry from the lower side,
Alternatively, if the carry is predicted to occur, effective address calculation will require at least two cycles, a normal effective address calculation cycle and an interlock cycle. Assuming that the address in each module is 32 bits, the case in which the above carry occurs is when an access that crosses the 4 gigabyte boundary occurs, and this kind of occurrence is extremely rare in actual data processing. Therefore, it does not become a factor that hinders the present invention.

Furthermore, if the effective address calculation module is divided into n parts, each module will detect the carry or predict the carry. When the carry is added to , the carry may occur again, so control is required to make the interlock cycle multiple cycles, but the frequency with which this happens also depends on actual data processing. Since it is considered to be small, it does not become a factor that hinders the present invention.

In this way, in the present invention, each divided module performs the effective address calculation shorter than the total address length in parallel, so the effective address calculation can be shortened and This has the effect of preventing the effective address calculation stage from becoming a time bottleneck, and eliminating the cause of processor performance deterioration.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

The above-mentioned FIG. 1 is a diagram explaining the present invention in detail, and FIG.
The figure shows an embodiment of the present invention, (a) shows a configuration example, (bl) to (b3) show operation time charts, and the effective address in a processor operating in a pipeline is shown. The calculation module, with respect to the effective address,
For example, if the module is divided into upper and lower parts and the effective address is calculated in parallel in each divided module, and a carry is detected on the lower side during the calculation process, or If it is predicted that A means for making the effective address of the address is a necessary means for carrying out the present invention. Note that the same reference numerals refer to the same objects throughout the plan.

Hereinafter, the effective address calculation method of the present invention will be explained with reference to FIG. 2 while referring to FIG.

In this embodiment, the total effective address bit length is 64
The effective address calculation module of the vibe line is divided into upper and lower 32 bits, respectively, with respect to the effective address, so that effective address calculation can be performed independently for each bit. Further, the effective address calculation will be explained as executing "base addresser displacement", for example.

First, assuming that the pipeline operation is executed in five stages, for example, as shown in the figure (bl), in the effective address calculation stage (AC), each module 1 inputs the input register (A-REG-U). /L) The contents of the pace register of the instruction are set in 11, and the input register (
The contents of the displacement are set in D-REG-'U/L) 12, and an effective address adder (EA) consisting of a known carry-hold adder (C5A) and a carry-propagate adder (CPA) is set.
GU/L) 13, the effective address is calculated.

When the effective address adder (EAG-U/L) 13 is configured in this way, a carry from a lower address can be monitored using a signal from the aforementioned look-ahead carry means. Further, by monitoring the carry using, for example, a signal from the above-mentioned look-ahead carry means made up of several upper bits, it is possible to predict the carry from the lower address.

In this way, when a carry occurs or a carry prediction signal occurs in the effective address calculation module 1 of the lower address, the carry holding register (CR) 14 of the upper effective address calculation module 1
is set to

(1) No carry If it is recognized that there is no carry from the lower effective address calculation module 1, the effective address calculation result in each module 1 is transferred from the effective address calculation stage (AC) to the operand fetch. At the time of stage (OF) transition, the effective address register (EA-REG-
U/L) is set to 15 and the set result is combined and used as the operand fetch address in the next operand fetch stage (OF). At this time,
There is no pipeline disturbance and normal pipeline operation occurs. (Refer to figure (b2)) (2) Carry 7 Carry predicted When a carry (or carry prediction) signal from the lower effective address calculation module 1 is detected, it is also sent to the pipeline control unit. Immediately, the interlock signal ■ is sent to each functional module including the upper effective address calculation module 1, and the carry adder (CEAG-[1)
At step 16, each functional module etc. is interlocked until the carry addition is completed.

This interlock cycle (IAC in this figure (b3))
Now, the lower effective address register (EA-REG-
L) 15 is locked and the lower effective address is held.

During this time, the upper effective address calculation module 1 performs a process of adding the carry to the calculation result of the upper effective address, that is, recalculates the upper effective address,
The result is passed through a multiplexer (MPX) 51 to
Upper effective address register (EA-REG-11)
It is reset to 15.

With this, the interlock cycle is released and normal pipeline operation is resumed. (See figure (b3)) In the above effective address calculation according to the present invention, if the carry prediction signal is used, there may be a case where "no carry" occurs, and in this case, the above interlock cycle is considered to be a wasteful process. However, the recalculation of the upper address is an addition of ``O'' (that is, a carry of 10), and the result is obtained normally.

In addition, in the above embodiment, an example was explained in which the effective address calculation module is divided into two effective address calculation modules 1 for upper and lower addresses, but the invention is not limited to this, and in general, multiple addresses It goes without saying that the bit may be divided into a plurality of units.

However, in this case, the effective address calculations are performed in parallel in the plurality of divided effective address calculation modules 1, and when a carry occurs in a certain module 1,
That is, each functional module is interlocked, and the process of adding the carry from the lower module 1 to the calculation result of the upper module in the upper module 1 is the same as above, but 1, a carry may occur again. In this case, the interlock ■ is applied again, the data is sent to the upper module 1, and the effective address is calculated in the upper module 1. This is necessary. And in any module 1,
If a carry does not occur, an additional control is required to release the interlock and return to normal pipeline operation, but such cases are extremely rare.
This does not become a factor that hinders the speeding up of effective address calculation by parallel calculation, which is an effect of the present invention.

As described above, the present invention provides an effective address calculation control method for a processor operating in a pipelined manner.
An effective address calculation module in a processor operating in a pipeline is divided into two, for example, upper/lower, with respect to the effective address, and each divided module calculates the effective address in parallel, and in the calculation process, interlocking the pipeline when a carry is detected or predicted;
The feature is that after adding the carry to the higher-order calculation result, the result is combined with the interlocked lower-order calculation result to form a true effective address.

〔Effect of the invention〕

As described above in detail, the effective address calculation control method in the pipeline processor of the present invention divides the effective address calculation module into a plurality of modules, for example, two modules, with multiple bits of the effective address as a unit. , calculate the effective address independently in each divided module and detect the presence or absence of a carry from the module sharing the lower address, or calculate the carry using the upper few bits of the lower module. If there is no such carry, continue the normal pipeline operation and combine the calculation results of each module until a carry from a lower module is detected or a carry is detected. If it is predicted that there is a carry, interlock the pipeline, add the carry to the calculation result of the upper module, and then combine that result with the calculation result of the interlocked lower module. Since the effective address is calculated in parallel in each divided module, the effective address calculation, which is shorter than the total address length, can be shortened, and all pipeline stages can be This has the effect of preventing the effective address calculation stage from becoming a time bottleneck in the process, and eliminating the cause of processor performance deterioration.

[Brief explanation of the drawing]

FIG. 1 is a diagram explaining the present invention in detail. FIG. 2 is a diagram showing an embodiment of the present invention. FIG. 3 is a diagram explaining an effective address calculation control method in a conventional pipeline processor. It is. In the drawing, 1 is a divided effective address calculation module. 11 is an input register (^-REc-U/L). 12 is an input register (D-REG-U/L). 13 is an effective address adder (EAG-U/L). 14 is a carry hold register (CR). 15 is effective address register (EA-REG-U/L)
. 16 is a carry adder (CEAG-U). ■ is an interlock signal. are shown respectively. Figure 1 (al)
(a2) Fig. 3 (Part 1) Mi ← 129 cycle time at X pit address → 1 (bl) 1 → 2X Bift 7 Tres I Temple d9 cycle time L ÷ 7 (b2) Fig. 3 (Part 2)

Claims (2)

[Claims] (1) In a processor that operates in a pipeline system, the effective address calculation module is divided into a plurality of modules (1) using multiple bits of the effective address as a unit, and each divided module (1) independently performs the following steps: The effective address is calculated and the presence or absence of a carry from each module (1) sharing the lower address is detected. If there is no carry, normal pipeline operation continues and each module The calculation results of (1) are combined, and if there is a carry, the pipeline is interlocked and each module ( An effective address calculation control method in a pipeline processor, characterized in that after repeating step 1) until there is no more carry, the result is combined with the interlocked lower calculation results to obtain an effective address. . (2) In a processor that operates in a pipeline system, the effective address calculation module is divided into a plurality of modules (1) using multiple bits of the effective address as a unit, and each divided module (1) independently performs the following steps: Calculate the effective address and predict a carry using the upper few bits of each module (1) that shares the lower address. If it is predicted that there will be no carry, continue normal pipeline operation. Then, the calculation results of each module (1) are combined, and if it is predicted that there will be a carry, the pipeline is interlocked and the calculation results of each upper module (1) are combined with the carry. Each module (1)
After repeating until there are no more carries, the result and
An effective address calculation control method in a pipeline processor, characterized in that the interlocked lower order calculation results are combined to form an effective address.