JPS585362U - Lead frame board - Google Patents

Lead frame board

Info

Publication number
JPS585362U
JPS585362U JP1981098744U JP9874481U JPS585362U JP S585362 U JPS585362 U JP S585362U JP 1981098744 U JP1981098744 U JP 1981098744U JP 9874481 U JP9874481 U JP 9874481U JP S585362 U JPS585362 U JP S585362U
Authority
JP
Japan
Prior art keywords
lead
lead frame
mounting
frame board
leads
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1981098744U
Other languages
Japanese (ja)
Other versions
JPS6218069Y2 (en
Inventor
細見　幸弘
Original Assignee
三洋電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三洋電機株式会社 filed Critical 三洋電機株式会社
Priority to JP1981098744U priority Critical patent/JPS585362U/en
Publication of JPS585362U publication Critical patent/JPS585362U/en
Application granted granted Critical
Publication of JPS6218069Y2 publication Critical patent/JPS6218069Y2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案のリードフレーム基板の一１例を示す正
面図、第２図Ａ、　Ｂは本実施例のＩＪ−ドフレーム基
板を用いて２個の発光ダイオードチップを並列接続した
発光ダイオード装置を示す平面図及び断面図、第３図Ａ
、　Ｂは本実施例のリードフレーム基板を用いて２個の
発光ダイオードチップを直列接続した発光ダイオード装
置を示す平面図及び断面図である。 ２、　４．　８・・・第１〜第３リード、３，９・・・
第１、第２載置部、６・・・基部、７・・・タイバー、
５・・・ボンディング部。Fig. 1 is a front view showing one example of the lead frame board of the present invention, and Figs. 2 A and B show a light emitting diode in which two light emitting diode chips are connected in parallel using the IJ-frame board of the present invention. Plan view and sectional view showing the device, Figure 3A
, B are a plan view and a sectional view showing a light emitting diode device in which two light emitting diode chips are connected in series using the lead frame substrate of this embodiment. 2, 4. 8...1st to 3rd leads, 3,9...
First and second mounting parts, 6... base, 7... tie bar,
5...Bonding part.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 一端に発光ダイオードチップを載置するための第１載置
部が形成され、該第１載置部より垂下する第１リードと
、一端にボンディング部が形成され該ボンディング部よ
り垂下する第２リードと、上記第１、第２リードの他端
に一体に形成された基部と、上記第１、第２リードの中
程において一体に形成され、斯る第１、第２リードの延
在方向と垂直となる方向に延在するタイバーと、一端に
発光ダイオードチップを載置するための第２載置部が形
成され該第２載置部より垂下すると共に他端が上記タイ
バーに一体に形成されている第３リードとからなること
を特徴とするリードフレーム基板。A first mounting part for mounting a light emitting diode chip is formed at one end, a first lead that hangs down from the first mounting part, and a second lead that has a bonding part formed at one end and hangs down from the bonding part. , a base integrally formed at the other ends of the first and second leads, and a base integrally formed in the middle of the first and second leads, and a base part integrally formed in the middle of the first and second leads, and A tie bar extends in a vertical direction, and a second mounting part for mounting a light emitting diode chip is formed at one end of the tie bar, and the other end is formed integrally with the tie bar. A lead frame board comprising a third lead.
JP1981098744U 1981-07-01 1981-07-01 Lead frame board Granted JPS585362U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1981098744U JPS585362U (en) 1981-07-01 1981-07-01 Lead frame board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1981098744U JPS585362U (en) 1981-07-01 1981-07-01 Lead frame board

Publications (2)

Publication Number Publication Date
JPS585362U true JPS585362U (en) 1983-01-13
JPS6218069Y2 JPS6218069Y2 (en) 1987-05-09

Family

ID=29893494

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1981098744U Granted JPS585362U (en) 1981-07-01 1981-07-01 Lead frame board

Country Status (1)

Country Link
JP (1) JPS585362U (en)

Also Published As

Publication number Publication date
JPS6218069Y2 (en) 1987-05-09

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