JPS5853528B2 - Interfering pulse suppression device for FM stereo receiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an interference prevention and Luz suppression device for an FM stereo receiver.

In this type of device, when performing stereo demodulation by sample-holding a stereo composite signal with a 381111z sample signal synchronized with the subcarrier, the stereo composite signal is sample-held as described above, and the hold output is
Further, a configuration has been separately proposed and filed in which interference pulses contained in a stereo composite signal are suppressed by sample-holding and stereo demodulation using a sample signal whose phase is delayed from that of the first sample signal.

FIG. 1 shows a specific example of this, in which the signal from the FM detection output or the stereo composite signal A from the intermediate frequency amplification circuit is amplified by an amplifier 1 and then synchronized with the pilot signal 3.
The signal is supplied to the subcarrier generator 2 for generating 8KIIz pulses a to d, and is also supplied to the first sample and hold circuits 3 and 4.

The sample-and-hold output of the sample-and-hold circuit 3.4 is further applied to second sample-and-hold circuits 5 and 6.

The outputs R and L from this are then averaged into an R signal and an L signal.

The sample-and-hold circuit 3 samples and holds, for example, an odd-numbered peak of the subcarrier in the stereo composite signal, using the 38 KHz pulse a synchronized with the pilot signal from the subcarrier generator 2 as a sample signal, and Using pulse b with a phase difference of 180 degrees as a sample signal, the sample-and-hold circuit 4 samples and holds the even-numbered peaks of the subcarriers in the stereo composite signal.

The sample-and-hold circuit 5 samples and holds the sample-and-hold value of the sample-and-hold circuit 3 using a pulse C whose phase lags that of the pulse a as a sample signal.

Further, the sample and hold circuit 6 is similar to the sample and hold circuit 4.
The sample and hold value of is sampled and held using pulse d whose phase is delayed from pulse b as a sample signal.

Pulses c and d are applied via gate circuits 7 and 8.

According to this configuration, interference pulses are removed as follows.

This will be explained about the sample and hold circuits 3 and 5 with reference to FIG. 2. As mentioned above, the sample and hold circuit 3 samples and holds the stereo composite signal A using the pulse a, and sends the output B.

The sample and hold circuit 5 further samples and holds this output B using a pulse C, and outputs an output R.

The output R has a phase that lags the output B by the phase lag of the pulse C with respect to the pulse a.

Now, if the stereo composite signal A contains an interference pulse P, then by sampling this with pulse a,
The output B has a level L corresponding to the peak value of the disturbance pulse P.
rises to.

On the other hand, the disturbance pulse P is detected by the abnormal pulse detector 9, and its detection output is sent to the gate circuit 7 or 8.

The gate circuit is normally open, but it is closed for a certain period of time by the detection output, so the output B
During the period when is at level L, pulse C is not applied to sample hold circuit 5, and therefore the previous sample hold value is continuously held.

This prevents the interference pulse P from appearing at the output R.

However, with this configuration, the following problem occurs when the level of the interfering pulse is abnormally high.

In other words, even if pulse a1 were able to sample the interference pulse P and the sample value of level L could be held in the output B, the next pulse a2 would produce the stereo composite signal A.
When sampling, because the interfering pulse is at an abnormally high level, it takes time for the hold capacitor to discharge for the output B to drop from the L level to the input level of the stereo composite signal at that time, and therefore this level The sample-and-hold circuit 3 samples and holds the stereo composite signal by the pulse a2 before the signal decreases to 1.

Therefore, although the output B should originally have the waveform shown by the dotted line in the figure, it becomes a waveform with a higher level than this, and this results in an error.

Correspondingly, the output R of the sample and hold circuit 5 should also have a waveform as shown by the dotted line in the figure, but it becomes a waveform of a higher level than this, which causes an error.

Such an error occurs even in the sample-and-hold operation by the sample-and-hold circuits 4 and 6, and the same can be said for negative interference pulses.

An object of the present invention is to reduce errors as much as possible when removing interfering pulses even when the level of the interfering pulses is high.

The present invention is characterized in that, when a disturbance pulse is detected, a sample-and-hold value of a sample-and-hold circuit at the next stage is given as an input to a sample-and-hold circuit that receives a stereo composite signal as an input, instead of the stereo composite signal. .

An embodiment of this invention will be explained with reference to FIG. 3 and subsequent figures.

Note that parts given the same reference numerals as in FIGS. 1 and 2 refer to the same or corresponding parts.

In FIG. 3, hold circuits 15 and 16 not only hold the stereo composite signal A via sample circuits 13 and 14, but also hold the outputs of sample and hold circuits 5 and 6 via sample circuits 11 and 12.

The sample circuit It, 12 samples the detection output produced when the abnormal pulse detector 9 detects an abnormal pulse, and causes the outputs of the sample and hold circuits 5 and 6 to be held in the hold circuits 15 and 16.

At this time, the hold circuits 15 and 16 are connected to the sample circuits 13 and 13.
In place of the stereo composite signal from 14, inputs from sample and hold circuits 5 and 6 are sampled and held by sample circuits 11 and 12 using detected output pulses from abnormal pulse detector 9.

In the above configuration, the sample circuit lL12°13.1
4. The sample and hold operation of the hold circuit 15.16 is as follows: 1. There is no particular difference from the case in Figure 1.

The operation when the interference pulse P is included in the stereo composite signal A will be explained with reference to FIG. 4. The interference pulse P is sampled and held by the pulse a1 and output from the hold circuit 15.

However, at this time, the abnormal pulse detector 9 detects the interference pulse P, so that the future Suisho pulse detection signal S
is input to the sample circuit 11 as a sample pulse, so the hold value of level L1 held by the sample hold circuit 5 at that time is input to the sample circuit 11.
12 and held in the hold circuit 15 in place of the interference pulse, which is the hold value at that time.

As shown in FIG. 4, the reason why the interference pulse P is held in the hold circuit 15 is that after the interference pulse P is sampled in the sample hold circuit 13 by the sample pulse a1, the output signal R of the sample hold circuit This is a short time until it is sampled by the pulse detection signal S in the sample and hold circuit 11 (see waveform B in FIG. 4).

). In this case, even if it takes time for the hold value at level L to decrease to level L1 due to input switching, there is enough time until the next pulse a2 is output, so during this time the hold circuit 15 It is possible to replace the hold value.

As a result, when the next pulse a2 is output, the output of the sample and hold circuit 3 has returned to the level L1 at the time of the previous sample and hold, so the sample and hold circuit is almost free from the error due to the pulse a2. Instead, the stereo composite signal that does not include any interfering pulses at that point in time is sampled and held.

As a result, almost no error occurs in the sample-and-hold value by the sample-and-hold circuit 5.

The sample and hold operations by the sample and hold circuits 4 and 6 are also similar.

In the configuration shown in FIG. 3, the sample-and-hold circuit 5 samples and holds the pulse c1 that is output immediately after the interference pulse appears, but when attempting to remove the interference pulse more reliably, the same method as in the case of FIG. 1 is used. It is also possible to provide gate circuits 7 and 8 to close the gate circuits 7 and 8 so that the pulses c and d immediately after the disturbance pulses are not applied to the sample and hold circuits 5 and 6.

FIG. 5 shows this configuration.

As described in detail above, according to the present invention, when removing a disturbance pulse, even if the level of the disturbance pulse sampled and held by the sample and hold circuit is abnormally high, by the time of the next sample, the previous sample and hold circuit is Since the sample hold value of is given as an input, it has the effect of easily avoiding errors that tend to occur in the previously proposed configuration.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an existing proposal, FIG. 2 is a time chart diagram for explaining the operation, and FIG. 3 is a circuit diagram showing an embodiment of the present invention.
FIG. 4 is a time chart for explaining the operation, and FIG. 5 is a circuit diagram showing another embodiment. 3.4...First sample and hold circuit, 5゜6...Second sample and hold circuit, 7,8...
...Gate circuit, 9...Abnormal pulse detector, 11,1213.14...Sample circuit,
15.16...Hold circuit, a, b...
...First pulse, C2d...Second pulse.

Claims (1)

[Claims] 1 a first sample-and-hold circuit that samples and holds a stereo composite signal with a first pulse of 38 degrees synchronized with a subcarrier; a second sample and hold circuit that samples and holds the second pulse, and when the stereo composite signal includes a disturbance pulse, the hold output of the second sample and hold circuit is replaced with the stereo compensation signal. A first sample and hold circuit that samples and holds a stereo composite signal with a first pulse of 38 KHz synchronized with a subcarrier; , said first
a second sample-and-hold circuit that samples and holds the hold output of the sample-and-hold circuit with a second pulse whose phase lags that of the first pulse, and when the stereo composite signal includes an interfering pulse, Said second
FM stereo, in which the hold output of the sample hold circuit is held in the first sample hold circuit instead of the stereo composite signal, and the sampling operation of the second sample hold circuit caused by the second pulse is stopped. Interference prevention and Luz suppression device for receivers.