JPS5917913B2 - Interference pulse suppression device for FM stereo receiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an interference pulse suppression device for an FM stereo receiver.

In an FM stereo receiver that performs stereo demodulation using a sample-and-hold method, when an interfering pulse is detected by an interfering pulse detection circuit, sampling/gaming is prohibited during that time, and the interfering pulse is suppressed.

The jamming pulse may be followed by a jamming pulse that is weaker than the detection level of the jamming pulse detection circuit. With respect to such a disturbance pulse, if uplinking is always prohibited only once, the suppression of the disturbance pulse will be insufficient. For this purpose, 9 pulses from the subcarrier generator are
．． By using a low frequency such as 5 KHZ or 4.75 HZ, this insufficiency can be overcome to some extent. However, according to this, sampling cannot be prohibited an arbitrary number of times, such as 2, 4, 8, etc., to a power of 2. Therefore, an object of the present invention is to provide a disturbance pulse suppression device that makes it possible to prohibit sampling an arbitrary number of times. After the pulse enters the counter circuit, sampling is resumed. An embodiment of the present invention will be described with reference to the drawings. In FIG. 1, 1 is an amplifier which amplifies the signal from the FM detection output.

2 is a subcarrier generator (e.g., phase-locked
(using a loop circuit) receives the amplified output (composite signal A) of amplifier 1 and generates a 38 KHz pulse synchronized with the pilot signal included in composite signal A.

That is, output terminal 3 outputs pulse B1 synchronized with one peak value of the subcarrier in composite signal A, output terminal 4 outputs pulse B2 synchronized with the other peak value, and output terminal 5 outputs pulse B1. A pulse C1 with a phase delay of, for example, 90 degrees is outputted from the output terminal 6, and a pulse C2 with a phase delay of, for example, 90 degrees from the pulse B2 is outputted from the output terminal 6. Further, the composite signal A is transmitted to the first sample and hold circuit 7,
8 is input.

Then, when the pulses B1 and B2 are applied as sampling signals to the first sample and hold circuits 7 and 8, respectively, the composite signal A is sampled and the sampled value is held. Furthermore, outputs D and E from these first sample and hold circuits 7 and 8 are input to second sample and hold circuits 9 and 10. SoU
2, the pulses Cl and C2 are input as sampling signals to the second sample and hold circuits 9 and 10 via the gate circuits 11 and 12, and the outputs D and E are sampled and the sampled values are held. The outputs F and G from the second sample and hold circuits 9 and 10 are averaged by a low-pass filter as an R or L channel signal, and sent to a speaker via a de-emphasis circuit or the like. moreover,
The composite signal A is input to the interference pulse detection circuit 13.

Then, a detection output for detecting the interference pulse is outputted, and the flip-flop 14 is set. In addition, the pulse H is output from the output 15 of the subcarrier generator 2 to the counter circuit 17.
The output of the counter circuit 17 is input to the reset terminal of the flip-flop 14. The detection output of the interference pulse detection circuit 13 is input to the clear terminal of the counter circuit 17. The pulse from flip-flop 14 is applied to gate circuits 11 and 12, and when applied, each gate circuit 11 and 12 is closed, blocking the passage of pulses Cl and C2. When the gate circuits 11 and 12 are open, the pulses Cl and C2 pass through the gate circuits 11 and 12 and are applied as sampling signals to the sample and hold circuits 9 and 10. FIG. 2 shows a waveform diagram of the output or signal of the circuit of FIG. 1, and each waveform symbol is shown to match the output or signal symbol in FIG.

With the above configuration, the composite signal A is applied to the sample and hold circuits 7 and 8, and the high and low peak values of the 38 KHz subcarrier are sampled and held using the sampling signals B1 and B2.

These operations are the same as when performing known stereo demodulation using the sample-and-hold method. This hold value is then given to sample and hold circuits 9 and 10, where it is sampled by sampling signals Cl and C2 and the sampled value is held. Then, the R or L channel signal is extracted from the hold value. For example, if a disturbance pulse P is included at the peak position of the subcarrier, the first sample and hold circuit 8 samples this disturbance pulse P and holds its peak value.
This hold value is input to the second sample and hold circuit 10.

On the other hand, the disturbance pulse P is detected by the disturbance pulse detection circuit 13, and the detection output clears the counter circuit 17 and sets the flip-flop 14. The gate circuit 12 is closed by the output pulse from the flip-flop 14, and the next sampling signal C2 is
A reset signal is input to the flip-flop 14, and passage is prohibited until the output pulse disappears and the gate circuit 12 is opened. Further, the counter circuit 17 starts counting the pulses H, and when a certain number is reached, the flip-flop 14 is reset by its output signal. As a result, the flip
Since the output pulse from the flop 14 disappears, the gate circuit 12 opens and the second sample and hold circuit 10 resumes sampling using the sampling signal C2. The operation of the present invention is the same even if the interfering pulse is included at the low peak of the subcarrier.

Further, even if the interference pulse is not a positive pulse as shown in the figure but a negative pulse, the interference pulse detection circuit detects this and the same operation is performed. As detailed above, the flip-flop that generates the pulse to prohibit sampling
Since the flop is reset by the output of the counter circuit, the inhibition of sampling can always be set to an arbitrary fixed number, which has the effect that interference pulses can be reliably suppressed and unnecessary sampling stops will not occur.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing an embodiment of the present invention, and Fig. 2 is a circuit diagram showing an embodiment of the present invention.
FIG.

Claims (1)

[Claims] 1. A subcarrier generator that generates a subcarrier from a pilot signal included in a stereo composite signal, a sample hold circuit that samples and holds the stereo composite signal in synchronization with the subcarrier, and an interference pulse detection circuit in the stereo composite signal. Then, the detection output of the interference pulse detection circuit is inputted to the set terminal of the flip-flop, and also inputted to the clear terminal of the counter circuit, and the output of the subcarrier generator is inputted to the counter circuit, and the output of the subcarrier generator is inputted to the counter circuit. a circuit that inputs the output of the flip-flop to the reset terminal of the flip-flop, and temporarily prohibits input of the sampling signal to the sample-and-hold circuit according to the output signal of the flip-flop. suppression device.