JPS5833734B2 - FM stereo demodulation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an FM stereo demodulation circuit, and particularly to a sample-and-hold FM stereo demodulation circuit.

As is well known, a general demodulation circuit directly separates and obtains an L signal and an R signal by switching the received composite signal with pulses synchronized with the subcarrier at a repetition frequency of 38 kHz. be.

By the way, the received subchannel (38KHz subcarrier) may contain abnormal pulses due to noise or other factors, and if this is demodulated as is,
Correct L or R signals cannot be obtained.

Therefore, when an abnormal pulse is detected in the sub-channel in the received composite signal, it is conceivable to override the lock and prevent it from entering the demodulation circuit during the period in which the abnormal pulse occurs.

However, according to this, the waveform of the subcarrier waveform appears to be stripped off during that period, so that an L or R signal with a distorted waveform is demodulated.

The same holds true even when the main channel contains abnormal pulses.

An object of the present invention is to demodulate a composite signal by minimizing its influence when an abnormal pulse is included in the composite signal.

This invention samples the subcarrier at the peak phase, holds it until the next sampling, and demodulates the composite signal by sample-holding and demodulating it using pulses with a repetition frequency of 38 KHz. When an abnormal pulse is included at each sampling time, the sampling at that time is stopped, and the hold value up to that point is continued to be held until the next sampling time.

An embodiment of the present invention will be described with reference to the drawings. 1 is an amplifier that inputs the detection output, 2 is a delay circuit provided as necessary, 3 and 4 are amplifiers, and 5 is a phase-locked loop (
PLL), the 19 KHz stereo pilot signal in the FM detection output is used as a comparison reference input, and the output frequency is controlled to 19 KHz. VCO
) 9 and frequency dividers 10, 11, and 12.

In this example, the oscillation frequency of the voltage controlled oscillator 9 is set to 152 KHz during stereo reception, and as a result of dividing the frequency into two by the frequency dividers 10 to 12, a frequency signal of 19 KHz from the frequency divider 12 is obtained. (This is synchronized with the pilot signal.

) is applied to the phase comparator 6.

As understood from the above description, the frequencies of the outputs of the branchers 10 and 110 are 76 KHz and 38 KHz.

Here, a sample timing pulse is obtained by logically processing signals of output frequencies of 152 KHz, 176 KHz, and 138 KHz from the voltage controlled oscillator 9 and each of the branching units 10 and 110, as well as four abnormal pulse detection signals to be described later.

Reference numeral 15 denotes an abnormal pulse detection circuit, which allows only bipulses to pass through a bypass filter 16 which inputs the output of the amplifier 1, which is detected by a pulse detector 17, and triggers a monostable circuit 18 with the detected pulse.

The metastable time of the monostable circuit 18 is set to a time shorter than half the period of the 19 KHz frequency signal.

The pulses emitted during the metastable time of the monostable circuit 18 are input to the inverting circuit 19.

20 and 21 are NAND circuits, both of which are voltage controlled oscillators 9.
The 152 KHz frequency output from the frequency divider 10, the 76 KHz frequency output from the frequency divider 10, and the output from the inversion circuit 19 are input to the NAND circuit 20.
The frequency output of KHz, and the NAND circuit 21 is the frequency divider 1.
The input is an inverted output (Q output) of a frequency of 1 to 38 KHz.

Each NAND circuit 20, 21 is applied as a timing pulse for sampling to sample hold circuits 22, 23 which receive the output of the amplifier 4 as an input.

24 and 25 are de-emphasis circuits, and 26 and 27 are amplifiers. The output of the amplifier 16 is given to the speaker as an L signal, and the output of the amplifier 27 is given as an R signal to the speaker.

Each sample hold circuit 22 23 is each NAND circuit 20
, 21, the output of the amplifier 4 at that time is sampled and held until the next sample.

FIG. 2 shows the output waveforms from the main parts of the configuration shown in FIG. 1, where a is the output (15
2KHz), b is the output of frequency divider 10 (76KHz),
C is the output (Q output) of the frequency divider 11 (38 KHz), d is the output (Q output) of the frequency divider 11, and e is the pulse detection circuit 17
, f is the output of the inversion circuit 19, g, h are the outputs of the NAND circuit 20゜21, m, n are the sample and hold circuit 22
゜230 output is shown.

As understood from the figure, the output of each frequency divider is frequency-divided in synchronization with the fall of the output a.

Further, the pulse width of the output a is set narrower than the pulse interval.

In the above configuration, in the case of stereo broadcasting, the output (composite signal) of amplifier 1 and therefore amplifier 3 has a frequency of 19 kHz.
The pilot signal is included, and at this time the output a=d
are 152 KHz and 76 KHz.

38 KHz, all of which are synchronized to the pilot signal.

Then, the rising or falling timing of the outputs c and d coincides with the positive and negative peak phases of the subcarrier in the composite signal.

On the other hand, the output g of the NAND circuit 20 is output because the output of the inverting circuit 19 is continuously "HI+" when no abnormal pulse is included in the subcarrier, and is output during the period when both c are rising. It falls when the output a rises, and rises when the output a falls.

Similarly, the output of the NAND circuit 21 falls when the output a rises during the period when both outputs d and d rise, and rises when the output a falls.

If the pulse during the falling period of the outputs g and h is used as a timing pulse for sampling, the rising timing of this pulse will be a 38 KHz pulse that coincides with the positive and negative peak phases of the subcarrier.

When the pulses g and h fall, each sample and hold circuit 22 and 23 samples and holds the output i of the amplifier 4.

Therefore, this sample and hold value samples and holds the L and R signals immediately before the peak phase of the subcarrier (strictly speaking, only the pulse of output a).

The sample value is held until the next fall of pulses g and h, at which point a new sample is taken.

When the composite signal is sampled and held as described above, the outputs m and n of the sample and hold circuits 22 and 230 are averaged through a low-pass filter, passed through de-emphasis circuits 24 and 25, and amplified by amplifiers 26 and 27, and then output to the speaker. sent to.

In the illustrated example, the output of the amplifier 26 is an L signal, and the output of the amplifier 27 is an R signal.

Now, assume that the output of the amplifier 4 contains an abnormal pulse P as shown in FIG.

The abnormal pulse P is previously detected by the bypass filter 16 and the pulse detector 17 which input the output of the amplifier 1, so that the pulse detector 17 outputs an output e.

This triggers the monostable circuit 18 and the inverting circuit 19
The output f from II is equal to the metastable time of the monostable circuit 18.
It becomes L.

Therefore, during this period, the NAND circuits 20 and 21 do not generate timing pulses even if all other inputs are applied.

The example in the figure shows a case where an abnormal pulse P is included during the sampling time by the NAND circuit 21, so
At this time, the sample hold circuit 23 does not sample.

Therefore, the hold value continues to be held as is the value held by the previous sample.

As a result, in the R signal from the amplifier 27, there is hardly any waveform distortion caused by the abnormal pulse P.

The same holds true when an abnormal pulse is included at the sampling timing by the NAND circuit 20.

Even if an abnormal pulse is included at a time other than the sampling timing by the NAND circuits 20 and 21, since sampling is not performed at this time, the outputs m and n will not contain this abnormal pulse.

In addition, since the abnormal pulse is included, the inversion circuit 1
When the output of 9 falls, the falling timing is the output c
, d may fall later than the falling time, so
When it is necessary to adjust this, a delay circuit 2 may be provided to delay the falling timing of the outputs c and d.

If delay adjustment is not required, the delay circuit 2 may not be provided.

As detailed above, according to the present invention, the composite signal is sampled and held at its peak phase in synchronization with the subcarrier, and when an abnormal pulse is included in the composite signal, this is detected. Since the sample is stopped and the previous sample value is held as it is, the obtained L and R signals will not be particularly affected by the above-mentioned abnormal pulse even if it is included in the composite signal. It has the effect of being absent.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a waveform diagram for explaining the operation. 5... Phase locked loop, 9...
・Voltage controlled oscillator, 10, 11, 12... Frequency divider, 15... Abnormal pulse detection circuit, 20, 21
...NAND circuit, 22, 23...Sample hold circuit, P...Abnormal pulse.

Claims (1)

[Claims] 1. During a phase-locked loop using the 19 KHz pilot signal in the stereo composite signal as the comparison reference input,
A voltage controlled oscillator whose output frequency is frequency locked to 152 KHz, the output of the voltage controlled oscillator is frequency locked to 76 KHz.
A 10th frequency divider divides the output of the 10th frequency divider into 3
A 20th frequency divider that divides the frequency into 8 KHz is provided, and the frequency division by each of the frequency dividers is synchronized with the falling edge of the 152 KHz output pulse, and the abnormal pulse included in the stereo composite signal is An abnormal pulse detection circuit that detects and outputs an output for a certain period of time is provided, and the voltage controlled oscillator, the first
and outputs the first timing pulse for sampling when the output of the 20th frequency divider is input, and at this time, when the output of the abnormal pulse detection circuit is input, the first timing pulse is output.
a first gate that does not output a timing pulse, and a second gate for sampling when the voltage controlled oscillator, the output of the 10th frequency divider and the inverted output of the 20th frequency divider are given as inputs.
When a timing pulse is output and the output of the abnormal pulse detection circuit is given at this time, the second gate does not output the second timing pulse, and the first and second gates
said stereo composite signal by a timing pulse of
An FM stereo demodulation circuit comprising: a sample hold circuit that samples and holds the sample until it is sampled by the next timing pulse; and a circuit that obtains R(No. 8) from the sample hold value of the sample hold circuit.