JPS5811144B2 - noise suppression circuit - Google Patents

noise suppression circuit

Info

Publication number
JPS5811144B2
JPS5811144B2 JP11706077A JP11706077A JPS5811144B2 JP S5811144 B2 JPS5811144 B2 JP S5811144B2 JP 11706077 A JP11706077 A JP 11706077A JP 11706077 A JP11706077 A JP 11706077A JP S5811144 B2 JPS5811144 B2 JP S5811144B2
Authority
JP
Japan
Prior art keywords
circuit
output
signal
gate
noise
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP11706077A
Other languages
Japanese (ja)
Other versions
JPS5450201A (en
Inventor
渡辺雅弘
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP11706077A priority Critical patent/JPS5811144B2/en
Publication of JPS5450201A publication Critical patent/JPS5450201A/en
Publication of JPS5811144B2 publication Critical patent/JPS5811144B2/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04HBROADCAST COMMUNICATION
    • H04H40/00Arrangements specially adapted for receiving broadcast information
    • H04H40/18Arrangements characterised by circuits or components specially adapted for receiving
    • H04H40/27Arrangements characterised by circuits or components specially adapted for receiving specially adapted for broadcast systems covered by groups H04H20/53 - H04H20/95
    • H04H40/36Arrangements characterised by circuits or components specially adapted for receiving specially adapted for broadcast systems covered by groups H04H20/53 - H04H20/95 specially adapted for stereophonic broadcast receiving
    • H04H40/45Arrangements characterised by circuits or components specially adapted for receiving specially adapted for broadcast systems covered by groups H04H20/53 - H04H20/95 specially adapted for stereophonic broadcast receiving for FM stereophonic broadcast systems receiving
    • H04H40/72Arrangements characterised by circuits or components specially adapted for receiving specially adapted for broadcast systems covered by groups H04H20/53 - H04H20/95 specially adapted for stereophonic broadcast receiving for FM stereophonic broadcast systems receiving for noise suppression
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B1/00Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06Receivers
    • H04B1/16Circuits
    • H04B1/1646Circuits adapted for the reception of stereophonic signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Noise Elimination (AREA)
  • Stereo-Broadcasting Methods (AREA)

Description

【発明の詳細な説明】 本発明はFMステレオ受信機等におけるパルス性雑音の
抑圧回路に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pulse noise suppression circuit in an FM stereo receiver or the like.

第1図は一般のFMステレオ復調回路の構成を示すもの
で、1は周波数弁別器の出力(コンポジット信号)が加
わる端子、2は端子1に加わったコンポジット信号に含
まれるパイロット信号と2分周器6の出力との位相を比
較する位相比較器、3は低域フィルタ、4はこの低域フ
ィルタ3の出力で発振周波数が制御される電圧制御発振
器、5は2分周器である。
Figure 1 shows the configuration of a general FM stereo demodulation circuit, where 1 is a terminal to which the output of the frequency discriminator (composite signal) is applied, 2 is the pilot signal included in the composite signal applied to terminal 1, and the frequency is divided by 2. 3 is a low-pass filter; 4 is a voltage-controlled oscillator whose oscillation frequency is controlled by the output of the low-pass filter 3; and 5 is a frequency divider by two.

7は2分周器5の出力を2分周し、2分周器6と同一周
期でかつ位相がπ/2遅れた信号を出力する2分周器、
8はパイロット信号と2分周器7の出力の位相を比較す
る位相比較器、9は低域フィルタ、10は直流増幅器、
11は直流増幅器10の出力レベルが一定値以上である
ときにはステレオ放送を受信したと判別し、以下である
ときにはモノラル放送を受信したと判別するステレオ検
知回路である。
7 is a 2-frequency divider which divides the output of the 2-frequency divider 5 by 2 and outputs a signal having the same period as that of the 2-frequency divider 6 and whose phase is delayed by π/2;
8 is a phase comparator that compares the phase of the pilot signal and the output of the 2-frequency divider 7; 9 is a low-pass filter; 10 is a DC amplifier;
Reference numeral 11 denotes a stereo detection circuit which determines that a stereo broadcast has been received when the output level of the DC amplifier 10 is above a certain value, and determines that a monaural broadcast has been received when it is below a certain value.

12は2分周器Iの出力を位相反転し、波形を矩形波か
ら正弦波に変換してコンポジット信号中のパイロット信
号と同一周期、同一レベルの逆相の信号を出力する位相
反転・波形変換回路、13はステレオ検知回路11の出
力により制御され、ステレオ放送時に開かれ、モノラル
放送時に閉じられるゲート回路、14はゲート回路13
の出力とコンポジット信号の和をとり、パイロット信号
成分を除去するパイロット信号除去回路である。
12 is a phase inversion/waveform conversion that inverts the phase of the output of the frequency divider I by 2, converts the waveform from a rectangular wave to a sine wave, and outputs an opposite phase signal with the same period and the same level as the pilot signal in the composite signal. A gate circuit 13 is controlled by the output of the stereo detection circuit 11 and is opened during stereo broadcasting and closed during monaural broadcasting; 14 is a gate circuit 13;
This is a pilot signal removal circuit that calculates the sum of the output and the composite signal and removes the pilot signal component.

15はステレオ放送時には左右チャンネル音声信号を分
離して出力し、モノラル放送時には周波数弁別器出力を
そのまま左右音声信号として出力するステレオ復調回路
、16.17はそれぞれ左、右ステレオ音声信号の出力
端子、18はステレオ表示ランプに接続される端子であ
る。
15 is a stereo demodulation circuit that separates and outputs left and right channel audio signals during stereo broadcasting, and outputs the frequency discriminator output as is as left and right audio signals during monaural broadcasting; 16 and 17 are output terminals for left and right stereo audio signals, respectively; 18 is a terminal connected to a stereo display lamp.

第2図は各部の信号波形を示すもので、aはコンポジッ
ト信号に含まれるステレオ信号、bはコンポジット信号
に含まれるパイロット信号、Cは電圧制御発振器4の出
力、d、e、fはそれぞれ2分周器5,6,7の出力、
gは回路12の出力である。
Figure 2 shows the signal waveforms of each part, where a is the stereo signal included in the composite signal, b is the pilot signal included in the composite signal, C is the output of the voltage controlled oscillator 4, and d, e, and f are each 2 Outputs of frequency dividers 5, 6, 7,
g is the output of circuit 12.

なおこの第1図および第2図で説明した復調回路は一般
的なもので、その動作についての説明は省略Xる。
Note that the demodulation circuit described in FIGS. 1 and 2 is a general one, and a description of its operation will be omitted.

この種のFMステレオ復調回路においてパルス性雑音を
除去する場合、周波数弁別器と復調回路との間に第3図
に示す雑音抑圧回路を設けている。
When removing pulse noise in this type of FM stereo demodulation circuit, a noise suppression circuit shown in FIG. 3 is provided between the frequency discriminator and the demodulation circuit.

第3図において、19は周波数弁別器に接続される端子
、20はステレオ復調回路へ接続される端子である。
In FIG. 3, 19 is a terminal connected to a frequency discriminator, and 20 is a terminal connected to a stereo demodulation circuit.

21はパルス性雑音を検出する雑音検出回路、22はゲ
ート制御信号を発生する回路23は周波数弁別器の出力
を一定時間遅延させる遅延回路、24は回路22のゲー
ト制御信号が加わった時に閉じるゲート回路、25はゲ
ート回路24が閉じている期間にそのゲート回路24が
閉じる直前の信号レベルを保持し、ゲート回路24が開
いている期間にはゲート回路24の出力をそのままバッ
ファ回路26に送るクランプ回路である。
21 is a noise detection circuit that detects pulse noise; 22 is a gate control signal generating circuit; 23 is a delay circuit that delays the output of the frequency discriminator for a certain period of time; and 24 is a gate that closes when the gate control signal of circuit 22 is applied. A circuit 25 is a clamp that holds the signal level immediately before the gate circuit 24 is closed while the gate circuit 24 is closed, and sends the output of the gate circuit 24 as it is to the buffer circuit 26 while the gate circuit 24 is open. It is a circuit.

この回路において周波数弁別器の出力中にパルス性の雑
音が含まれていた場合、雑音検出回路21がその雑音を
検出し、回路22を駆動してその雑音に対応するゲート
制御信号を発生する。
In this circuit, if pulse noise is included in the output of the frequency discriminator, the noise detection circuit 21 detects the noise and drives the circuit 22 to generate a gate control signal corresponding to the noise.

また雑音を含んだコンポジット信号は遅延回路23で遅
延され、ゲート制御信号とタイミングが合わされた状態
でゲート回路24に加えられる。
Further, the composite signal containing noise is delayed by a delay circuit 23 and applied to a gate circuit 24 in a state in which the timing is matched with the gate control signal.

ゲート制御信号24の加わっている期間だけゲート回路
24は閉じ、クランプ回路25はゲート回路24が閉じ
る直前の出力を継続して出力し、信号が中断することを
防止している。
The gate circuit 24 is closed only during the period when the gate control signal 24 is applied, and the clamp circuit 25 continues to output the output immediately before the gate circuit 24 was closed, thereby preventing the signal from being interrupted.

しかしこの場合法の問題が生じる。However, legal issues arise in this case.

すなわち雑音が加わっている期間、クランプ回路25に
おいて信号レベルは一定値に保たれているにもかかわら
ず、FMステレオ復調回路に設けられたパイロット信号
除去回路においてパイロットと同一周期同一振巾の逆相
の信号が加わるため、この信号が復調された左右チャン
ネル音声信号に重畳されて出力され、新たな雑音となる
In other words, even though the signal level is maintained at a constant value in the clamp circuit 25 during the period when noise is added, the pilot signal removal circuit provided in the FM stereo demodulation circuit generates a signal with the same period and amplitude as the pilot but with an opposite phase. Since this signal is added, this signal is superimposed on the demodulated left and right channel audio signals and output, creating new noise.

本発明はこの問題を解決するもので、以下にその実施例
について説明する。
The present invention solves this problem, and examples thereof will be described below.

第4図において符号2〜12.14〜19,21〜26
はそれぞれ汗1図および第3図における同符号のものに
対応する。
In Figure 4, the numbers 2-12, 14-19, 21-26
correspond to the same reference numerals in Figures 1 and 3, respectively.

27は位相反転・波形変換回路12の出力を伝送するこ
とを制御するためのゲート回路、28はクランプ回路で
ある。
27 is a gate circuit for controlling the transmission of the output of the phase inversion/waveform conversion circuit 12, and 28 is a clamp circuit.

次にこの実施例要部の動作について説明する。Next, the operation of the main parts of this embodiment will be explained.

ステレオ信号が受信され、かつパルス性の雑音が検出回
路21で検出されていない状態においてはゲート回路2
7は開かれる。
When a stereo signal is received and pulse noise is not detected by the detection circuit 21, the gate circuit 2
7 will be opened.

したがって位相反転・波形変換回路12の出力はゲート
回路27を介してクランプ回路に加わり、そのまま出力
されてステレオ復調回路15に加えられて通常のステレ
オ復調動作が行なわれる。
Therefore, the output of the phase inversion/waveform conversion circuit 12 is applied to the clamp circuit via the gate circuit 27, and is output as is and applied to the stereo demodulation circuit 15 for normal stereo demodulation operation.

ところが、モノラル放送を受信している時あるいはパル
ス性雑音が検出回路21で検出された時にはゲート回路
27が閉じる。
However, when a monaural broadcast is being received or when pulse noise is detected by the detection circuit 21, the gate circuit 27 is closed.

したがってクラシブ回路28はゲート回路21が閉じる
直前の信号を保持し、出力される。
Therefore, the classic circuit 28 holds and outputs the signal immediately before the gate circuit 21 closes.

なおこの場合にモノラル放送を受信した時には必ずしも
直前のレベルをクランプ回路で保持しておく必要はない
In this case, when a monaural broadcast is received, it is not necessarily necessary to hold the previous level in the clamp circuit.

このようにして雑音発生時にコンポジット信号に含まれ
たパイロット信号を除去するための信号がパイロット信
号除去回路に加わらないため、雑音の発生を防止できる
In this way, since the signal for removing the pilot signal included in the composite signal is not applied to the pilot signal removal circuit when noise occurs, the generation of noise can be prevented.

以上の説明から明らかなように本発明によればコンポジ
ット信号に含まれた雑音を確実に除去でき、また雑音抑
圧中に従来のパイロット信号発生回路で混入していた不
要成分を除去することができる。
As is clear from the above description, according to the present invention, it is possible to reliably remove noise contained in a composite signal, and also to remove unnecessary components mixed in by a conventional pilot signal generation circuit during noise suppression. .

【図面の簡単な説明】[Brief explanation of drawings]

第1図はFMステレオ復調回路のブロック図、第2図は
その信号波形図、第3図は従来の雑音抑圧回路のブロッ
ク図、第4図は本発明の一実施例による雑音抑圧回路の
ブロック図である。 12・・・・・・位相反転・波形変換回路、14・・・
・・パイロット信号除去回路、21・・・・・雑音検出
回路、23・・・・・・遅延回路、24,27・・・・
・ゲート回路、25.28・・・・クランプ回路。
FIG. 1 is a block diagram of an FM stereo demodulation circuit, FIG. 2 is a signal waveform diagram thereof, FIG. 3 is a block diagram of a conventional noise suppression circuit, and FIG. 4 is a block diagram of a noise suppression circuit according to an embodiment of the present invention. It is a diagram. 12... Phase inversion/waveform conversion circuit, 14...
... Pilot signal removal circuit, 21 ... Noise detection circuit, 23 ... Delay circuit, 24, 27 ...
・Gate circuit, 25.28...clamp circuit.

Claims (1)

【特許請求の範囲】[Claims] 1 周波数弁別器の出力に含まれたパルス性の雑音を検
出する検出回路、上記周波数弁別器の出力を一定時間遅
延させる遅延回路、上記検出回路で雑音を検出した時に
上記遅延回路の出力の伝送を停止させる第1のゲート回
路、この第1のゲート回路が閉じている時には閉じる直
前の信号レベルを保持して出力し、開いている時には上
記第1のゲート回路の出力を通過させる第1のクランプ
回路、上記周波数弁別器の出力に含まれたパイロット信
号のキャンセル用信号を発生する発生回路、上記検出回
路で雑音を検出した時に上記発生回路の出力の伝送を停
止する第2のゲート回路、この第2のゲート回路が閉じ
ている時には閉じる直前の信号を保持して出力し、開い
ている時には上記第2のゲート回路の出力を通過させる
第2のクランプ回路、およびこの第2のクランプ回路の
出力と上記第1のクランプ回路の出力とを入力するパイ
ロット信号除去回路を設けた雑音抑圧回路。
1. A detection circuit that detects pulse noise included in the output of the frequency discriminator, a delay circuit that delays the output of the frequency discriminator for a certain period of time, and transmission of the output of the delay circuit when the detection circuit detects noise. a first gate circuit that stops the first gate circuit; when this first gate circuit is closed, it outputs while maintaining the signal level immediately before closing, and when it is open, a first gate circuit that allows the output of the first gate circuit to pass through; a clamp circuit, a generation circuit that generates a signal for canceling the pilot signal included in the output of the frequency discriminator, a second gate circuit that stops transmission of the output of the generation circuit when the detection circuit detects noise; a second clamp circuit that holds and outputs the signal immediately before closing when the second gate circuit is closed; and a second clamp circuit that allows the output of the second gate circuit to pass when the second gate circuit is open; A noise suppression circuit comprising a pilot signal removal circuit inputting the output of the first clamp circuit and the output of the first clamp circuit.
JP11706077A 1977-09-28 1977-09-28 noise suppression circuit Expired JPS5811144B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11706077A JPS5811144B2 (en) 1977-09-28 1977-09-28 noise suppression circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11706077A JPS5811144B2 (en) 1977-09-28 1977-09-28 noise suppression circuit

Publications (2)

Publication Number Publication Date
JPS5450201A JPS5450201A (en) 1979-04-20
JPS5811144B2 true JPS5811144B2 (en) 1983-03-01

Family

ID=14702424

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11706077A Expired JPS5811144B2 (en) 1977-09-28 1977-09-28 noise suppression circuit

Country Status (1)

Country Link
JP (1) JPS5811144B2 (en)

Also Published As

Publication number Publication date
JPS5450201A (en) 1979-04-20

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