JPS5823982B2 - FM stereo receiver noise suppression circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a noise suppression circuit that suppresses noise when pulse noise is superimposed on a received signal of an FM stereo receiver.

The following methods are conventionally known as noise pulse suppression methods for FM stereo receivers.

(1) A switch circuit and a hold circuit are installed between the frequency discriminator and the stereo demodulator. 1 Normally, the switch circuit is turned on to allow the signal to pass. If noise is detected, the switch circuit is turned off during that time and the signal is passed. This method uses a hold circuit to hold the signal level just before the switch circuit turns OFF by stopping the passage of the signal.

(2) A method in which a switch circuit and a clamp circuit are provided after the stereo demodulation circuit, similar to the method (1) above.

The present invention differs from the above-mentioned systems in that the stereo demodulation circuit uses a sample-and-hold method, and noise suppression is also performed in the demodulation circuit, thereby simplifying the configuration and ensuring noise suppression. There is.

Embodiments of the present invention will be described below with reference to FIGS. 1 to 4.

In FIG. 1, 1 is the composite signal 5(t) (LR) sin2πf t in the frequency discriminator output T.
(1) (However, L is the left channel audio output, R is the right channel audio output, and P is the pilot signal amplitude.

f5 is a high-pass filter that passes signals having frequency components higher than the upper limit frequency of the subcarrier frequency (38 [Glz)), and obtains the output shown in FIG. 2C.

Note that the cutoff frequency is set to around 100 KIIz.

2 is an amplifying and rectifying circuit that amplifies and rectifies the output of the high-pass filter 1; and 3, when the output of the amplifying and rectifying circuit 2 exceeds a certain level, this is determined to be a noise pulse.

The moment the output exceeds a certain level, the output becomes "0".

Output until the level falls below a certain level and a certain period of time τH has elapsed.
0" is maintained, and the output is 1 during other times. Figure 2 d
This is a gate pulse generation circuit that generates the signal shown in FIG.

Note that the delay time from the leading edge of the noise pulse to the moment of falling of the gate pulse is τ.

shall be. 1 to 3 described above constitute a noise pulse detection circuit.

4 is the pilot signal SP2.4 in the frequency discriminator output. SP
3. SP4. This is a sample pulse generating circuit which outputs SF3 (however, this is stopped while the output of the gate pulse generating circuit 3 is "0"), and the configuration of one circuit is shown in FIG.

Here, the sample pulse generation circuit 4 in FIG. 3 will be explained.

14 is a 19 KHz tuning circuit that extracts the pilot signal shown in FIG. 4a from the frequency discriminator output S (t).

It is assumed that FIG. 4 shows the subcarrier (38 KHz), and the phase relationship between the two signals is as shown in the figure.

15 is a phase comparator which uses the output of the 19 KHz tuning circuit 14 as one comparison input and the output of a flip-flop 19 (described later) as the other comparison input; 16 designates the output of the phase comparator 15 as the output signal of the VCO 17 (described later). Low-pass filter 17 converts into phase (frequency) control voltage; 17 is low-pass filter 1;
6, the phase of the output signal (
The VCO 118, whose frequency is controlled, operates at the rising edge of the output signal of the VCO 17, and is a flip-flop that divides the output by two to generate the output shown in FIG. 4d.

Reference numeral 19 denotes a flip-flop which operates at the rising edge of the output signal of the flip-flop 18 and divides its output by two, generating the output shown in FIG. 4e.

Note that the above components 15 to 19 constitute a PLL, and the phase relationship of each signal in the locked state is as shown in FIG. 4 a''-e.

20 is output 〃1〃 at a certain time τ1 from the rise time of ■C017 as shown in Fig. 4f.

During other times, the monostable multivibrator outputs "0", and 21 outputs "1" when the output of the monostable multivibrator 20 falls, as shown in FIG. 4g.

22 is an AND gate that allows the output of the differentiating circuit 21 to pass only while the output of the gate pulse generation circuit 3 (Figure 4 and Figure 2 d) is "1". , 23 is a monostable multi-by-break which outputs a sample pulse SP1 whose τ2 output is 1 for a certain period of time from the moment the output of the AND gate 22 becomes 1, and whose output is /10 for the rest of the time.

FIG. 4i and FIG. 2e are the output waveforms.

Here, the output pulse width τ1 of the monostable multi-bi break 20 and the output pulse width τ2 of the monostable multi-bi break 23 are 1 to 2 μsec.
c is appropriate) by setting the trailing edge of the output pulse of the monostable multivibrator 23, that is, the pulse SP1
The timing sin 2πf when the sample operation of the sample hold circuit 6, which is controlled by
, t-±1.

24 is a monostable multivibrator whose output τ3 is 1 for a certain period of time from the moment the output of the AND gate 22 becomes ``1'', and the output is ``0'' during the rest of the time, and Figure 4 j shows its output waveform. It is something.

Here, the relationship between the constant time τ3, the gate pulse delay time Tp holding time τ□ of the gate pulse generation circuit 3, and the pulse width τ2 of SP1 must be as follows.

τ2+τ.

kuτ3〈τ□ ・・・・・・・・・(2)25
is a monostable differential circuit whose output is "1" instantaneously at the fall of the output of the multi-by-break 24, and whose output is "0" during other times, and FIG. 4 shows its output waveform.

26 is an AND gate that allows the output of the differentiating circuit 25 to pass only while the output of the gate pulse generation circuit 3 is "1", and 27 is an AND gate that allows the output of the AND gate 26 to become "1" as shown in FIG. 4I. A monostable multi-by-break whose τ21 output is 1" for a certain period of time and 0 during other times; 28 is an inverter that inverts the phase of the output of the flip-flop 18; 29 is an inverter that inverts the phase of the output of the flip-flop 19. , 30 is an AND gate that allows the output pulse of the monostable multivibrator 27 to pass only while the output of the inverter 28 and the output of the flip-flop 19 are "1", and the output of this circuit is as shown in Figures 4m and 2. is 5in2πf5t- of the sample pulse generation circuit
1 and a pulse train SP2 delayed by a fixed time τ3 of the pulse train SP2.

31 is the output of the flip-flop 18 and the inverter 2
It is an AND gate that allows the output pulse of the monostable multivibrator 27 to pass only while the outputs of 9 are both "1",
As shown in FIG. 4n, the output of this circuit is the SP, 5i
The pulse train SP4 is delayed by n2πf8t=-1 and by a fixed time τ3 of the pulse train.

32 is a monostable multi-bi break 27 only when the output of the inverter 28 and the output of the inverter 29 are both 1.
This is an AND gate that passes the output pulse of SP, and the output of this circuit as shown in FIG.
A pulse train SP3 is obtained in which fst = 1 and delayed by a fixed time τ3 of the pulse train.

33 is an AND gate which passes the output pulse of the monostable multi-bi break 27 when the output of the flip-flop 18 and the output of the flip-flop 19 are both "1", and as shown in FIG. The pulse train SP is delayed by a fixed time τ3 of the pulse train that falls at the 5in2πf5t stage of the sample pulse generation circuit.

The above is the configuration and operation of the sample pulse generation circuit 4.

Returning to FIG. 1 again, 5 is the sample pulse SP shown in FIG. 2 e and FIG. 4 i that is being output from the sample pulse generation circuit 4.
1 is the opening wave number discriminator output (see Figure 2 a, b,
However, a indicates a composite signal on which a noise pulse is superimposed, and b indicates a 19 KHz pilot signal.

Therefore, the frequency discriminator output becomes a + b signal).

During the other periods, it is a sample hold circuit that holds the level sampled immediately before.

The output of this circuit when no noise pulse is superimposed is as follows.

5in2πf5t =-)-1 and 5in2πf, t = +1 and 5in2πf5t = -1 and 5in2πf5t = -1, and when a noise pulse is superimposed as shown in Fig. 2g, the noise pulse B as shown in Fig. 2f, The sample pulse SP1 is not generated while C is being output, so no sampling is performed during this period, and the output of this circuit is not affected by noise.

On the other hand, a sample pulse SP is generated as a gate pulse due to the noise pulses A and D, and the influence of this noise pulse appears as the output of this circuit.

Note that the portion where this influence remains is removed without being sampled by the sample-and-hold circuits 6 to 8 connected to the rear stage of this circuit.

In addition, the output of this circuit for the 19 imaginary pilot signal component is shown in Figure 2g.
It will be like this.

Therefore, the output waveform of this circuit is the sum of the solid lines f and g in FIG.

Reference numeral 6 designates a sample hold circuit which samples and holds the output of the sample hold circuit 5 using a sample pulse SP2 shown in FIG. 4m.

This circuit uses 5ln2π in the output of sample hold circuit 5.
The signal formula (4A) obtained by folding f by 2+1 is expressed as τ for a certain period of time.
The sample will be held 3 times late.

The outputs of this circuit are shown in Fig. 2 i and j.

However, i is the output signal waveform when the pilot signal component is removed, and j is the output waveform of only the pilot signal component.
In reality, it takes the form i+j.

7 shows the output of the sample and hold circuit 5 in Fig. 2 K and Fig. 4 0.
This is a sample hold circuit that samples and holds the sample pulse SP3 shown in FIG.

This circuit is a 5in2π output from the sample hold circuit 5.
The signal formula (4B) obtained by fst=+1 and - is sampled and held after a fixed time τ3.

The output waveform of this circuit has the form of the sum of 1 and m in FIG.

8 shows the output of the circuit 5 in FIG. 4n.

This is a sample hold circuit that samples and holds the sample pulse SP4.

This circuit is a 5in2 output of the sample hold circuit 5.
πf, t=-1 and the held signal equation (4C) is sampled and held after a fixed time τ3.

9 is a sample pulse SP whose output from circuit 5 is shown in FIG. 4P.
.

This is a sample-and-hold circuit that samples and holds the sample.

This circuit uses sin 2 in the output of the sample hold circuit 5.
ytf 5t =-1 and the held signal (formula 4B) is sampled and held after a fixed time τ3.

10 is a summation circuit which sums the output of circuit 6 and the output of circuit 7, and its output is shown in FIG.

(However, the output level of this circuit is (i+j+l+m in Figure 2)
/2).

That is, as is clear from the figure, the noise pulse is not superimposed on the main output, and the pilot signal component is also canceled out and is no longer output.

11 is a summation circuit 1 that sums the output of circuit 8 and the output of circuit 9;
2 is a low-pass filter that passes only the signal component in the audio frequency band output from the circuit 10;

This output becomes the left channel audio output.

Reference numeral 13 denotes a low-pass filter that passes only the signal component in the audio frequency band output from the summation circuit 11, and the output of this circuit becomes the right channel audio output.

That is, with the above configuration, pulse noise contained in the output of the frequency discriminator is detected by the high-pass filter 1 and rectified and amplified by the single circuit 2.

When the output of this circuit 2 reaches a predetermined level or higher, it is determined that it is noise that should be removed, and a gate pulse is generated from the circuit 3.

The sample pulse generating circuit 4 generates sample pulses SP, .about.SP, which have different phases, but stops generating the sample pulses when the gate pulse is generated.

The output of the frequency discriminator is first sampled and held using this sample pulse SP1, and this output is added to circuits 6 to 9, respectively.The output of each circuit 6 to 9, which is sampled and held at SP2 to SP, respectively, contains pulse noise. Since the configuration is configured such that the previously sampled output is generated when there is a problem, and a new sample and hold is performed during a period when no noise is added, so that the influence of noise can be removed.

The outputs of circuits 6 and 7 are summed by summation circuit 10, and filter 1
In step 2, the audio signal of the left channel is obtained by extracting the signal of only the audio band.

Similarly, the output of the summation circuit 11 is applied to the filter 13 to obtain the right channel audio signal.

As is clear from the above embodiments, according to the present invention, the 19KHz pilot signal component can be removed without providing a 19KHz wrap circuit for removing the 19KHz pilot signal in the front stage of the stereo demodulation circuit as in the conventional device. In addition, pulse noise can be suppressed more effectively than in the conventional example.

Furthermore, since the residual subcarrier component after stereo demodulation is smaller than the stereo demodulated output by the conventional switching method, it is easy to remove the component.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a noise suppression circuit of an FM stereo receiver according to an embodiment of the present invention, FIG. 2 is a signal waveform diagram thereof,
FIG. 3 is a block diagram showing the detailed configuration of the main parts, and FIG. 4 is a signal waveform diagram thereof. 1... High-pass filter, 4... Sample pulse generation circuit, 5 to 9... Sample hold circuit, 10°11... Sum circuit.

Claims (1)

[Claims] 1. A first sample and hold circuit that samples and holds the output of the frequency discriminator at a timing of 5in2πf, t-±1, and an output of this first sample and hold circuit that samples and holds the output of the frequency discriminator at a timing of 5in2πf, (-τ). =1 and 5in2πf 8(
t-r) = 1 and 5in2π, f, (t-?:
)=1 and s+n2πf 5 (t T)
2. Sample and hold each sample and hold at the timing when = '. a first summation circuit that sums the outputs of the third, fourth, and fifth sample-and-hold circuits; and the fourth and third sample-and-hold circuits; A second sum circuit that sums the output of the fifth sample and hold circuit, a detection circuit that detects pulse noise, and a detection circuit that detects pulse noise for a certain period of time (τN + τH) including the period (τN) during which the pulse noise is detected. 1st. 1. A noise suppression circuit for an FM stereo receiver, comprising: a control circuit for stopping generation of sample pulses applied to the second, third, fourth, and fifth sample-and-hold circuits. However, f, - subcarrier frequency τH in composite signal - holding time τ d constant time τH〉τ