JPS5833732B2 - Interference pulse suppression device for FM stereo receiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an interference pulse suppression device for an FM stereo receiver.

In general, in m receivers, to suppress interference pulses,
A gate circuit is usually provided between the gate waveform circuit and the stereo demodulation circuit, and this gate circuit is controlled by the detection output from the interference pulse detection circuit to prevent interference pulses from entering the stereo demodulation circuit. .

On the other hand, it is known that stereo demodulation is performed using a sample-and-hold method, and even in this case, sampling is stopped in response to a detection output from an interfering pulse detection circuit in order to suppress interfering pulses.

However, according to this, it is necessary to delay the FM detection output through a delay circuit before inputting it to the demodulation circuit, and if there is no delay circuit, the gate circuit will close after the interfering pulse passes through the gate circuit. become.

The delay circuit therefore delays the jamming pulse so that it is timed to arrive at the gate circuit after the gate circuit has closed.

Incidentally, this type of delay circuit generally uses a plurality of capacitors.

However, in order to use a capacitor in an integrated circuit, it is necessary to attach it externally, and it is not desirable for the integrated circuit to use a plurality of elements that require external attachment in this way.

This invention eliminates the use of delay circuits that require external connection,
The purpose of the present invention is to use a digitally configured circuit to suppress interference pulses so that they will not be demodulated, and also to have this circuit function as a demodulation circuit, thereby simplifying the construction of an interference pulse suppression circuit. .

This invention synchronizes a stereo composite signal to three subcarriers.
Sample and hold with an 8 KHz pulse train, then sample and hold this sample and hold value with another 38 KHz pulse that is out of phase with the pulse train, and from this hold value, obtain both R signals. and when it contains a disturbance pulse, the detection output from the disturbance pulse detection circuit samples the first or the first one and several subsequent sample-hold values of the latter pulse train that correspond to the disturbance pulse. It is configured so that the generation of pulses is stopped and sampling is not performed.

An embodiment of the present invention will be described with reference to the drawings. A signal from an FM detection output is amplified by an amplifier 1.

In response to this amplified output (composite signal) A, a subcarrier generator (for example, a phase-locked loop LLP) 2 generates a 38 KHz pulse synchronized with the pilot signal.

That is, the output terminal 3 outputs a pulse B1 synchronized with one peak value of the subcarrier in the composite signal A, the output terminal 4 outputs a pulse B2 synchronized with the other peak value, and the output terminal 5 outputs a pulse B1 synchronized with the peak value of one of the subcarriers in the composite signal A.
The composite signal A outputs a pulse C1 with a phase delay of, for example, 90 degrees from the pulse B1, and a pulse C2 with a phase delay of, for example, 90 degrees from the pulse B2 from the output terminal 6. It is input to circuit 7°8.

and pulse B1. When B2 is given as a sampling signal, the composite signal is sampled and the sampled value is held.

Further, the output from this, E, is input to second sample and hold circuits 9 and 10.

When the gate circuits 11 and 12 receive the sampling signal, they sample the hold value and hold the sample value.

The outputs F and G are averaged by a low-pass filter as an R signal and sent to a speaker via a de-emphasis circuit or the like.

The composite signal A is further input to the interference pulse detection circuit 13.

When a disturbance pulse is detected here, a detection output is output,
Trigger the monostable circuit 15 via the gate circuit 14 .

The width of the pulse from the monostable circuit 15 is set to a time corresponding to a phase angle of 90 degrees or more for a 38 KHz pulse.

However, this means that pulses C1 and C2 are pulse B1. This is the case when the phase is delayed by 90 degrees with respect to B2, and the point is that when an interfering pulse is detected, it is set to include at least the time when the first pulse C1 or C2 is generated. Ru.

The pulse from the monostable circuit 15 is given to the gate circuits 11 and 12, and when this is given, each gate circuit 11,
12 is closed and prevents the passage of pulses C1 or/and C2.

When gate circuits 11 and 12 are open, pulse C1
, C2 pass through gate circuits 11 and 12 and are applied to sample and hold circuits 9 and 10 as sampling signals.

°Goo 1 circuit 14 pulses B1. When an output is given from the OR circuit 16 which inputs B2, it opens and the detection circuit 1
Allow the detection output from 3 to pass through.

FIG. 2 shows a waveform diagram of the output or signal of the circuit in FIG. 1,
Each waveform symbol is shown to match the output or signal symbol in FIG.

In the above configuration, the composite signal A is given to the sample and hold circuits 7 and 8, and the high and low peak values of the subcarrier of 38]EG(z are sampled and held by the sampling signals B1 and B2.

These operations are the same as when performing known stereo demodulation using the sample-and-hold method.

This hold value is then stored in sample and hold circuits 9 and 10.
Here, it is sampled with sampling signals C1 and C2 and held.

Then, the R or L signal is extracted from the hold value.

For example, suppose that an interfering pulse P is included at the peak position of the subcarrier.

Then, the sample-and-hold circuit 8 samples this interference pulse P, holds its peak value, and outputs this to the sample-and-hold circuit 10.

On the other hand, the interference pulse P is detected by the interference pulse detection circuit 13.

At this time, pulse B2 is input to the OR circuit 14, so
The gate circuit 14 is opened by the output, the monostable circuit 15 is triggered by passing the detection output, and the output pulse enters the gate circuit 12.

Therefore, the gate circuit 12 is closed, and the passage of the next sampling signal C2 is blocked while the gate circuit 12 is closed.

Therefore, at the time of generation of this sampling signal C2,
The output from the sample-and-hold circuit 8 is not sampled, and the hold value continues to be held as it is until the next generation of the sampling signal C2.

If the output pulse of the monostable circuit 15 has not been completed between the time it is triggered and the first sampling signal C1 is generated, the output of the sample and hold circuit 7 is sampled by the sampling signal C1 as usual. , is held.

The above operation works in the same way even if the interfering pulse is included at the low peak of the subcarrier.

Further, even if the interference pulse is not a positive pulse as shown in the figure but a negative pulse, the interference pulse detection circuit 13 detects this, thereby performing the same operation as the rabbit.

By the way, although the above explanation was about the case where the interfering pulse is included at the peak of the subcarrier, it may be included between the peaks, for example, as the interfering pulse y.

At this time, it is not sampled because it is shifted from the generation timing of pulse B1 or B2.
Such a disturbance pulse y is also detected by the disturbance pulse detection circuit 13.

If the gate circuit 14 were not present, the monostable circuit 15 would be triggered by the detection output, so that the gate circuit 11.12 would then be closed for a certain period of time, blocking the passage of the pulses C1, C2.

Therefore, if a pulse C1 or C2 is generated during this blocking period, the part that should be sampled will not be sampled due to this pulse.

However, the gate circuit 14 is provided, and the pulse B1. If the gate circuit 14 is opened to allow the detection output to pass when the output of the OR circuit 16 whose input is B2 is given, then only when pulse B1 or B2 occurs, that is, the peak of the subcarrier. Only when the gate circuit 14 is open is the detection output allowed to pass through.

Therefore, due to the inclusion of the interference pulse y,
Even if a detection output is output from the interference pulse detection circuit 13,
At this time, pulse B1. Since B2 is not output, it will not pass through the gate circuit 14, and therefore the monostable circuit 15 will not be triggered.

Therefore, sampling using pulses C0 and C2 will be performed as usual.

As described in detail above, according to the present invention, when suppressing interference pulses, by not using a conventional delay circuit, elements that require external attachment such as capacitors are not required, and therefore integrated circuits In addition to having a suitable circuit configuration, it also has a sampling function for the demodulation circuit using the sample-and-hold method, which makes the circuit configuration extremely simple, operates accurately, and prevents interference at times other than the peak of the subcarrier. Even if pulses are included, this has the effect of preventing erroneous sampling.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a waveform diagram for explaining the operation. 2... Subcarrier generator, 7, 8...
First sample and hold circuit, 9, 10... Second sample and hold circuit, 11, 12, 14...
... Gate circuit, 13 ... Interfering pulse detection circuit, 15 ... Monostable circuit, 16 ... --- OR circuit.

Claims (1)

[Claims] 1. A first sample and hold circuit that samples and holds the stereo composite signal in synchronization with the peak of the subcarrier;
The hold value by the first sample and hold circuit is
a second sample-and-hold circuit that samples and holds a sampling signal whose phase lags behind the peak of the subcarrier and demodulates R and L signals from the held value; a circuit that detects an interference pulse in the stereo composite signal; Consisting of a gate circuit that allows the detection output from the circuit to pass through only during the first sample hold, and a circuit that prohibits input of the sampling signal to the second sample hold circuit for a certain period of time based on the output from the gate circuit. Interference pulse suppression device for FM stereo receiver.