JPH06338812A - Noise elimination circuit - Google Patents

Abstract

PURPOSE:To accurately hold a level just before detecting the pulse noise of an FM tuner IC. CONSTITUTION:A differentiation circuit 32 outputs difference between a delay signal 55 in which a composite signal 54 is delayed by a delay circuit 31 and the inverse signal of a pilot cancellation signal 56 from an inversion amplifier 39. Such output 59 is always written on memory 71 via an A/D converter 72. When a noise detection circuit 34 detects no pulse noise in the composite signal 54, a switch 74 is connected to a difference circuit 32 side, and a signal in which a pilot signal is eliminated from the composite signal 54 is outputted as it is by the difference circuit 32. When the noise detection circuit 34 detects the pulse noise, the switch 72 is switched to a D/A converter 73 side by the rising of a gate signal from a monostable multivibrator 35, and also, a value just before detecting the pulse noise is read out from the memory 71, and is outputted via a D/A converter 73 and a switch 74.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse noise removing circuit for an FM radio receiver.

[0002]

2. Description of the Related Art Generally, an FM radio receiver takes various measures against noise to improve sound quality. Among them, in an FM radio receiver for a vehicle, for example, pulse-shaped ignition noise coming from an engine often causes a problem, and various noise removing circuits for eliminating this have been proposed and used. Hereinafter, a general configuration of the conventional FM receiver and a pulse noise removing circuit will be described.

FIG. 2 shows a schematic configuration of a tuner IC of a general FM radio receiver. Antenna 11
The FM wave received at is input to the FM tuner IC 10, first amplified by the high frequency amplifier (RF AMP) 12, and then mixed by the mixer (MIX) 14 with the output of the local oscillator (L.OSC) 13 to obtain 10 0.7 MHz
Is converted to an intermediate frequency signal (IF) and amplified by an intermediate frequency amplifier (IF AMP) 15. Intermediate frequency amplifier 1
The output of 5 is detected by the FM detection circuit (FM DET) 16, and this detection output (composite signal 54) is input to the noise canceller 17. Noise canceller 17
Pulse noise is removed from the detection output of the FM detection circuit 16 and is input to the FM multiplexer 18. The FM multiplexer 18 separates the output of the noise canceller 17 into stereo signals of the left channel (L) and the right channel (R) by the matrix method, and outputs the stereo signals.

FIG. 5 shows the FM tuner IC shown in FIG.
It represents a conventional noise canceller used in the. This noise canceller 117 has an FM
The composite signal 54 is input from the detection circuit 16.
As shown in FIG. 3, the composite signal 54 is a signal in which a sum signal (L + R) of the L channel signal and the R channel signal, a difference signal (LR), and a pilot signal of 19 KHz are superimposed. Specifically, the difference signal (LR)
Are superimposed in the form of amplitude-modulated 38 kHz sub-signal.

The composite signal 54 is input to the noise detection circuit 34 via a high pass filter (HPF) 33. When the noise detection circuit 34 detects pulse noise from the output of the HPF 33, it outputs a noise detection signal and supplies it to the monostable multivibrator 35. The monostable multivibrator 35 supplies a gate signal having a pulse width determined by a time constant circuit composed of the capacitor 24 and the resistor 25 to the switch 36. The switch 36 is in an on (closed) state in a normal state, but is in an off (open) state during a gate signal input (“H” level), and is turned on again when the gate signal returns to “L” level. It is supposed to come back.

On the other hand, the composite signal 54 is delayed by the delay circuit 31 by the same delay time as the circuit operation from the HPF 33 to the switch 36. Delay circuit 31
The delayed signal 55 output from the (+) terminal of the difference circuit 32 in which the capacitor 37 is connected between the (+) terminal and the (−) terminal.
While being input to the terminal, it is also input to the pilot signal extraction circuit 21 of FIG. Here, the capacitor 37 is actually externally attached to the tuner IC via two external terminals. The pilot signal extraction circuit 21 uses the delayed signal 5
5 to 19 KHz pilot signal 57 is extracted and PL
It is supplied to the L (phase locked loop) circuit 22, and based on this, the PLL circuit 22 generates and outputs the pilot cancellation signal 56 of 19 KHz and the stereo demodulation signal 58 of 38 KHz.

The stereo demodulation signal 58 from the PLL circuit 22 is supplied to the FM multiplexer 18, and the sum signal (L
It is used to separate the difference signal (LR) superimposed on + R). Then, the sum signal (L + R) and the difference signal (L
Stereo signals L and R are output by taking the sum and difference of −R).

On the other hand, the pilot cancel signal 56 from the PLL circuit 22 is sent to the switch 36 via the buffer amplifier 39 of the noise canceller 117 as shown in FIG.
Is supplied to one of the terminals. As mentioned above, switch 3
Since 6 is closed when there is no pulse noise, 19
The KHz pilot cancel signal 56 is applied to the (−) terminal of the difference circuit 32 in phase with the 19 kHz stereo pilot signal in the composite signal 54. Therefore, in this case, the output 60 of the difference circuit 32 is the delay circuit 31.
From the output of the pilot signal 57, ie, only the sum signal (L + R) and the difference signal (LR).

On the other hand, when pulse noise is detected, the switch 36 is opened, and the pilot cancel signal 56 is not input to the (-) terminal of the difference circuit 32. in this case,
Since the (−) terminal of the difference circuit 32 is in a floating state, the potential of the (−) terminal is equal to the displacement amount of the potential of the (+) terminal due to the presence of the capacitor 37 connected between both terminals of the difference circuit 32. It changes by the same amount. Therefore, even if pulse noise is input to the (+) terminal, the level difference between both terminals is only the DC component accumulated in the capacitor 37, and the output holds the value V _K immediately before pulse noise detection. Therefore, assuming that the output of the delay circuit 31 has, for example, the waveform shown in FIG.
Assuming that the gate opening time of the switch 36 is tg, the waveform of the output 60 of the difference circuit 32 is as shown in FIG. That is, the pulse noise component is removed together with the pilot signal 57.

[0010]

As described above, in the conventional pulse noise removing circuit, the level is maintained immediately before the pulse noise is detected by the capacitor 37 connected between both terminals of the difference circuit 32. During this period, the capacitor 37 was discharged, and there was a problem that the level could not be held accurately.

Further, since the capacitor is externally attached to the tuner IC, two dedicated external terminals are required.
For this reason, the number of pins of the IC is increased and it is difficult to reduce the size of the IC. Further, since the step of attaching the capacitor to the IC is required, it has been a factor of increasing the manufacturing cost.

The present invention has been made in order to solve the above problems, and it is possible to accurately hold the level immediately before the detection of the pulse noise and to eliminate the pulse noise without providing the tuner IC with a dedicated external terminal. Aim to get the circuit.

[0013]

A pulse noise removing circuit according to the present invention is a noise removing circuit for removing a pilot signal and pulse noise from a composite signal obtained by FM detection of an intermediate frequency signal. i) a delay circuit that delays the composite signal for a predetermined time, (ii) a difference circuit that takes the difference between the output of this delay circuit and the pilot cancel signal synchronized with the pilot signal included in this output, and (iii) this difference Storage means for storing the output of the circuit,
(iv) detecting means for detecting pulse noise from the composite signal; (v) reading means for reading data stored in the storing means in response to pulse noise detection by the detecting means; and (vi) the In response to the detection of the pulse noise by the detecting means, the output of the difference circuit is switched to the output of the reading means for a predetermined time, and the output value of the difference circuit output value read from the storage means is output. Means and are provided.

[0014]

In the pulse noise removing circuit according to the present invention, the output of the difference circuit is output as it is when no pulse noise is detected, and is always stored in the storage means. On the other hand, when pulse noise is detected, the output from the storage means is output. The value immediately before pulse noise detection is read and output.

[0015]

The present invention will be described in detail below with reference to the drawings.

FIG. 2 shows a schematic configuration of a tuner IC including a noise removing circuit according to an embodiment of the present invention. In this figure, the same parts as those in the conventional example (FIG. 5) are designated by the same reference numerals, and the description thereof will be omitted as appropriate.

The overall operation of the FM tuner IC 10 is almost the same as that of the conventional example. That is, the FM wave received by the antenna 11 is first amplified by the high frequency amplifier 12, then mixed with the output of the local oscillator 13 by the mixer 14, converted into an intermediate frequency signal of 10.7 MHz, and further by the intermediate frequency amplifier 15. Is amplified. The output of the intermediate frequency amplifier 15 is detected by the FM detection circuit 16, and the detected output is input to the noise canceller 17 as the composite signal 54. The noise canceller 17 removes pulse noise from the detection output of the FM detection circuit 16, and the FM multiplexer 18 uses the matrix method to
The left channel (L) and right channel (R) channels are separately output as stereo signals.

FIG. 1 shows the structure of the noise canceller in FIG. 2 in detail. FM detection circuit 1 in the previous stage
As shown in FIG. 3, the composite signal 54 input to the noise canceller 17 from 6 (FIG. 1) is the sum signal (L + R) and difference signal (LR) of the L and R channels, and 19
The pilot signal of KHz is superimposed, which is the same as that described in the conventional example.

The composite signal 54 is input to the noise detection circuit 34 via a high pass filter (HPF) 33. When the noise detection circuit 34 detects pulse noise from the output of the high-pass filter 33, the noise detection signal 8
1 is output and supplied to the monostable multivibrator 35. The monostable multivibrator 35 includes a capacitor 24.
The gate signal 38 having a pulse width determined by the time constant circuit composed of the resistor 25 and the resistor 25 is supplied to the read enable terminal of the memory 71 and the switch 74. This switch 74 is used for the difference circuit 32 when no noise pulse is detected.
Is switched to the side of the D / A converter 73 at the same time as the rising of the gate signal 38, and this state is maintained during the input (“H” level) of the gate signal, and the gate signal is When it returns to the "L" level, it returns to the differential circuit 32 side again.

On the other hand, the composite signal 54 is input to the (+) terminal of the difference circuit 32 as a delay signal 55 delayed by the delay circuit 31 by the same time as the delay time by the operation circuit from the HPF 33 to the switch 74. , Into the pilot signal extraction circuit 21 of FIG.
The pilot signal extraction circuit 21 uses the delayed signals 55 to 19
PLL circuit 22 by extracting pilot signal 57 of KHz
Supply to. From the PLL circuit 22, a pilot cancel signal 56 synchronized with the pilot signal 57 is output, and is input to the (−) terminal of the difference circuit 32 via the buffer amplifier 39 of the noise canceller 17.

The difference circuit 32 takes the difference between the delay signal 55 and the pilot cancel signal 56 and switches 7
4 and analog digital (A / D)
Input to the converter 72. Therefore, the output 59 of the difference circuit 32 is obtained by removing the pilot signal from the output of the delay circuit 31, that is, the sum signal (L + R) and the difference signal (L-).
R) only. The A / D converter 72 uses the difference circuit 3
The analog output 59 of 2 is constantly monitored, converted into a digital value, and written in the memory 71.

When the noise detection circuit 34 does not detect pulse noise in the composite signal, the output 74 of the difference circuit 32 becomes the output 60 as it is because the switch 74 is switched to the side of the difference circuit 32 as described above. .

On the other hand, when the noise detection circuit 34 detects pulse noise, the switch 72 is switched to the D / A converter 73 side at the rising timing of the gate signal 38 from the monostable multivibrator 35, and the memory The output 59 of the difference circuit 32 immediately before the detection of the pulse noise is read from 71 and converted into an analog value by the D / A converter 73. This analog value does not include pulse noise, of course, and is output via the switch 72. Therefore, the output period t of the gate signal 38
The output of the difference circuit 32 immediately before the detection of the pulse noise is held over g, and the pulse noise is removed. Moreover,
Since the output content in this case is a value read from the memory 71, it takes an accurate constant value and does not cause a level drop due to discharge of the capacitor as in the conventional case. The output of the D / A converter 73 may be generated other than when the pulse noise is detected. In that case, there is no problem because the switch 72 selects the difference circuit 32.

The memory 71 is a so-called bi-CMOS.
It is easy to form in a single tuner IC by using a process, and in this case, external terminals can be reduced, but it goes without saying that the memory 71 can be provided outside the IC.

[0025]

As described above, according to the present invention, the output of the differential circuit is output as it is when no pulse noise is detected and is constantly stored in the storage means, while it is output from the storage means when pulse noise is detected. Since we decided to read and output the value immediately before pulse noise detection,
The value immediately before the detection of the pulse noise can be held constant during the period in which the pulse noise is limited.

[Brief description of drawings]

FIG. 1 is a block diagram showing a pulse noise removing circuit according to an embodiment of the present invention.

FIG. 2 is a diagram showing a schematic configuration of a general FM tuner IC.

FIG. 3 is an explanatory diagram showing frequency characteristics of a composite signal input to a pulse noise removal circuit.

FIG. 4 is an explanatory diagram showing an example of waveforms of a composite signal input to a pulse noise removal circuit and an output signal from the pulse noise removal circuit.

FIG. 5 is a block diagram showing a conventional pulse noise removal circuit.

[Explanation of symbols]

 10 FM tuner IC 11 antenna 12 high frequency amplifier 13 local oscillator 14 mixer 15 intermediate frequency amplifier 16 FM detection circuit 18 FM multiplexer 17 noise canceller 22 PLL circuit 31 delay circuit 32 difference circuit 34 noise detection circuit 35 monostable multivibrator 71 memory 72 A / D converter 73 D / A converter 74 Switch

Claims (1)

[Claims] 1. A noise removing circuit for removing a pilot signal and pulse noise from a composite signal obtained by FM detecting an intermediate frequency signal, the delay circuit delaying the composite signal for a predetermined time, and the delay circuit. A differential circuit that takes the difference between the output of the differential signal and the pilot cancel signal synchronized with the pilot signal included in the output, a storage unit that stores the output of the differential circuit, and a detection unit that detects pulse noise from the composite signal, In response to the detection of the pulse noise by the detecting means, the reading means for reading out the data stored in the storage means, and in response to the detection of the pulse noise by the detecting means, the reading out from the output of the difference circuit for a predetermined time. Switching to the output of the means and outputting the difference circuit output value read from the storage means A pulse noise elimination circuit comprising: output switching means;