JP3681147B2 - Television receiver having diversity function - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a television receiver having a diversity function.
[0002]
[Prior art]
A mobile object such as an in-vehicle television receiver installed or used in a vehicle has a function of performing diversity as an anti-multipath method, and realizes an automatic tracking operation to a reception environment.
A receiver that performs spatial diversity operation with a plurality of antennas is provided with a switching unit that can selectively switch the reception of the output from these antennas. Control is performed so that the level of the received television signal is detected, and the antenna that obtains the highest level among the detected levels is finally selected and confirmed by the switching unit. Here, the antenna switching in such control is preferably performed during the vertical blanking period of the television signal. This is because there is a signal that is responsible for the image information that is actually displayed in the portion other than the vertical blanking period in the television signal. If level detection or antenna switching is performed in this portion, noise ( This is because it appears as white and slender noise.
[0003]
However, it is difficult to say that good results can be obtained even if the diversity operation is performed only under such consideration.
The television receiver reproduces and outputs both the image and the sound. If the antenna is switched for the spatial diversity operation so that only the image is reproduced with high quality, the switching noise is generated in the sound. On the other hand, there is a possibility that the voice quality is lowered. Even if such switching noise does not occur, there may be an adverse effect that the image quality actually given to the viewer does not change or is reduced due to the spatial diversity operation.
[0004]
As described above, there is still room for technical efforts on how to optimize the antenna switching mode in terms of quality for the actual viewer of the entire reproduction information including audio in addition to images. It has been done.
[0005]
[Problems to be solved by the invention]
Therefore, the present invention has been made in view of the above points, and the main object of the present invention is to perform an optimal diversity operation in terms of quality for the actual viewer of the entire reproduction information including audio. It is to provide a television receiver.
[0006]
[Means for Solving the Problems]
A receiver according to an aspect of the present invention is a television receiver that performs a diversity operation according to a reception state, a demodulating unit that demodulates a composite video signal and an audio signal from a received signal, and vertical synchronization in the composite video signal Vertical timing detection means for detecting signal timing, distortion detection means for determining that the distortion of the audio signal has exceeded a predetermined level and generating a distortion detection signal, and timing detected by the vertical timing detection means On the basis of Video diversity operation, ie In response to the first diversity operation and in response to the distortion detection signal Voice diversity operation, ie And a control means for executing the second diversity operation. The control means prohibits the video diversity operation for a predetermined period after the distortion detection signal is generated. It is characterized by that.
[0007]
In the receiver of this aspect ,Previous The first diversity operation and the second diversity operation further include a loop detection unit that detects a state in which the reception modes opposite to each other are selected and the reception mode continues to be alternately repeated, and the control unit includes: The second diversity operation may be prohibited when a loop is detected.
[0008]
Furthermore, the distortion detection means may include differentiation means for detecting a steep increase in distortion component of the audio signal, and the distortion detection signal may be generated based on a differential output of the differentiation means.
In each of the above-described aspects, the distortion detection means includes a band-pass filter to which the audio signal is supplied, an amplitude detection circuit to which an output signal of the band-pass filter is supplied, and an output signal waveform of the amplitude detection circuit. A differentiating circuit for extracting a rising component of the differential circuit, and a comparator for comparing the extracted component level of the differentiating circuit with a reference value and generating a distortion detection signal that is significant when the extracted component level is greater than the reference value; , Can also be provided.
[0009]
The first and second diversity operations can be limited to a spatial diversity operation in which one of a plurality of reception antennas is selected and the reception mode is changed accordingly.
In addition, holding means for holding identification information of a receiving antenna to be selected can be provided, and the control means can change the holding contents of the holding means in response to the distortion detection signal.
[0010]
Further, in the first diversity operation, evaluation of the reception mode can be started from the reception mode by the reception antenna corresponding to the identification information held in the holding means.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 shows a schematic configuration of a diversity television receiver according to an embodiment of the present invention.
In FIG. 1, this receiver is of a type that is used while being moved, such as an in-vehicle receiver, and includes four receiving antennas ANT1 to ANT4 for realizing spatial diversity or these received signals. Connected to the output end, each antenna is electrically coupled to a switch (RF-SW) 1. The switch 1 selects any one of the four antennas, and supplies an RF (Radio Frequency) signal from the selected antenna to the video signal reproduction system 2 as a received signal.
[0012]
The video signal reproduction system 2 serves as a demodulating means, and a tuner (not shown) as a front end that converts a reception signal from the switch 1 into an intermediate frequency signal, and a video intermediate frequency amplifier 21 that amplifies the intermediate frequency signal, And an AM detection circuit 22 for reproducing the composite video signal by demodulating the intermediate frequency signal amplified by the amplifier 21 by AM (Amplitude Modulation). The composite video signal is supplied to a CRT (Cathode-Ray Tube) 2x as a display device through various reproduction circuits and amplification circuits (not shown). The CRT 2x displays an image corresponding to the composite video signal. As the display device, a liquid crystal display or the like can be applied in addition to the CRT.
[0013]
The received signal supplied to the video intermediate frequency amplifier 21 includes an audio signal in addition to the video signal. The audio intermediate frequency signal is taken out by the video intermediate frequency amplifier 21 and supplied to the audio signal reproduction system 3. The audio signal reproduction system 3 includes an audio intermediate frequency amplifier 31 that amplifies the audio intermediate frequency signal, an FM (Frequency Modulation) demodulation of the intermediate frequency signal amplified by the amplifier 31, and an FM detection circuit 32 that reproduces a composite audio signal. including. The composite audio signal is supplied to a speaker 3x as an acoustic output device through various reproduction circuits and amplification circuits (not shown). The speaker 3x makes an acoustic output corresponding to the composite audio signal.
[0014]
The composite video signal from the video signal reproduction system 2 is supplied to the waveform shaping circuit 41 and the control unit 5 while the level of the sync chip is made constant by the clamp circuit 40.
The waveform shaping circuit 41 generates a composite synchronization signal including only various synchronization signals and a blanking signal except for a component (hereinafter referred to as “video signal” where appropriate) that carries pure video information from the supplied composite video signal. This is supplied to a low-pass filter (LPF) 60. The LPF 60 eliminates the 2fH component (fH is the horizontal sync frequency) due to the equalization pulse in the composite sync signal, and attenuates the high frequency component of the composite sync signal. Therefore, a signal corresponding to the frequency component of fH is obtained from the output of the LPF 60. The output of the LPF 60 is supplied to one input terminal of the phase comparator 61. The phase comparator 61 compares one input signal with the other input signal and outputs a phase error signal corresponding to the phase difference between the two to the LPF 62. The phase error signal that has passed through the LPF 62 is supplied to a VCO (Voltage-Controlled Oscillator) 63 as a control signal.
[0015]
The VCO 63 has a center frequency of 32 fH, oscillates with a deviation from the center frequency according to the supplied control signal, and supplies the oscillation output signal to the control unit 5 and the frequency divider 64. The frequency divider 64 divides the oscillation output signal from the VCO 63 to generate a signal having a frequency of fH and supplies it to the other input terminal of the control unit 5 and the phase comparator 61. The phase comparator 61, the LPF 62, the VCO 63, and the frequency divider 64 form a so-called phase locked loop (PLL), follows the horizontal synchronizing frequency of the received composite video signal, and synchronizes with the horizontal synchronizing signal of the composite video signal. Generate a clock signal.
[0016]
The composite synchronization signal from the waveform shaping circuit 41 is also supplied to the inverting circuit 81. The composite synchronizing signal inverted by the inverting circuit 81 is supplied to one input terminal of the level comparator 83 via the LPF 82. The comparator 83 compares the output signal of the LPF 82, that is, the integrated output of the composite synchronizing signal, with the reference voltage level Vr, and generates a signal that becomes a high level only when the output signal of the LPF 82 exceeds the reference voltage level Vr. Is supplied to the control unit 5. Since the generated high level signal has a frequency (fv) equivalent to that of the vertical synchronizing signal, the vertical synchronizing signal is detected from the composite synchronizing signal by the inverting circuit 81, the LPF 82 and the comparator 83 (hereinafter referred to as the vertical synchronizing signal). The output signal of the comparator 83 is called an equivalent vertical synchronizing signal).
[0017]
The composite audio signal from the audio signal reproduction system 3 is also supplied to the distortion detection circuit 3A. The distortion detection circuit 3 </ b> A detects distortion due to multipath of the composite audio signal with sensitivity according to the sensitivity adjustment signal, and supplies a signal according to the detection level to the control unit 5. The composite audio signal includes each channel signal and control signal for supporting stereo broadcasting and bilingual broadcasting.
[0018]
The control unit 5 is also supplied with a detection signal generated by an antenna non-connection detection circuit built in the switch (RF-SW) 1. The antenna non-connection detection circuit identifies which of the antennas ANT1 to ANT4 is not connected to the switch based on the internal signal of the switch 1, and generates a detection signal corresponding to the identification result as antenna connection information. To do.
[0019]
The control unit 5 can be configured by a microcomputer or the like, and controls each unit of the receiver based on the supplied signal and given information.
Such control includes a process of selecting an optimum receiving antenna based on detection of a pedestal level in the vertical blanking period of the composite video signal, and a QV pulse generating process for starting the antenna selecting process. In the antenna selection process, the control unit 5 supplies the antenna switching signals SEL1 to SEL4 to the switch 1, and the switch 1 reproduces the output of any one of the antennas ANT1 to ANT4 in accordance with the antenna switching signal. Relay to system 2.
[0020]
A QV pulse generation circuit for starting the antenna selection process is shown in FIG.
In FIG. 2, the QV pulse generation circuit 50 and its peripheral circuits are formed in the control unit 5. The QV pulse generation circuit 50 includes four D-type flip-flops 500 to 503, an AND circuit 504, NOT circuits 505 and 506, and a predetermined number of D-type flip-flop groups 509.
[0021]
The clock generator 65 divides the 32 fH master clock input from the VCO 63 to generate a clock signal having a period of 1 / (2 fH). The equivalent vertical synchronizing signal fv input to the QV pulse generation circuit 50 is sampled by the D flip-flops 500 to 503 at the cycle of the 2fH clock signal. At this time, since the equivalent vertical synchronizing signal fv is already binarized by the comparison means 83, each D flip-flop samples either a signal indicating a low level (L) or a high level (H). Will be.
[0022]
The D flip-flops 500 to 503, the NOT circuit 505, and the AND circuit 504 detect the generation of the vertical synchronization signal using continuous sample data in order to suppress erroneous detection of the vertical synchronization signal due to noise or the like.
The operation will be described below.
This circuit according to this embodiment is based on the assumption that the received signal is of the NTSC system, and is the first time when the outputs of the D flip-flops 503, 502, 501, and 500 become L, H, H, and H, respectively. The high-level Q pulse indicating the detection of the vertical synchronization signal is output from the AND circuit 504.
[0023]
This is shown in the waveform diagram of FIG.
When an equivalent vertical synchronizing signal is generated as shown in the figure, each input of the AND circuit 504 becomes a high level and a Q pulse is output during the period length of the 2fH clock signal corresponding to the triangle mark in the figure.
The generated Q pulse is delayed by a predetermined time in the D flip-flop group 509 and output as a QV pulse. This predetermined time corresponds to the time from the detection of the Q pulse until the antenna selection process is actually started. In this example, the predetermined time is 3.5 periods of the 2fH clock signal.
[0024]
In the present embodiment, as an example, a configuration in which D flip-flops 500 to 503 are used and four D flip-flops are used is shown. However, if it is desired to further suppress false detection, the D flip-flop used here is used. It is effective to further increase the number.
In the case of a multiplex broadcast wave, there is a possibility that the multiplex broadcast signal is superimposed after the sixth equalization pulse period from the end of the vertical synchronization signal as shown by a dotted line in the composite synchronization signal in FIG. A QV pulse, which is a start signal for the process, is output in order to complete the antenna selection process described below before the multiplex broadcast signal superimposing unit.
[0025]
The QV pulse obtained as described above is used as an activation signal for the antenna selection process described below.
FIG. 4 shows the configuration of the antenna selection processing circuit. This circuit has a function of starting an antenna selection process as a diversity operation in response to a QV pulse, and is formed in the control unit 5.
[0026]
In FIG. 4, the composite video signal from the AM detection circuit 22 is supplied to an A / D (analog / digital) converter 510. The A / D converter 510 digitally converts the composite video signal at each sampling timing specified by the timing control unit 511 and sends the digital output to the determination circuit 513.
[0027]
Note that the A / D converter 510 applied to the present embodiment is set so that the resolution in digital conversion is roughly 2 dB or more in terms of the antenna reception level. This is due to the following reason.
That is, even if the antenna has a reception level higher than the reception level of the currently selected antenna, if the level difference is within about 2 dB, there is almost no visual improvement in the reproduced image. It has been found that maintaining the current antenna without switching is more advantageous in terms of noise to the voice system. Thus, it was concluded that diversity antenna switching control does not require A / D conversion of the pedestal level of the composite video signal with high resolution.
[0028]
Therefore, in this embodiment, the resolution of A / D conversion for converting the pedestal level into a digital value is converted to the antenna reception level and set to 2 dB or coarser, and the antenna is not switched when the reception level is slightly higher. Thus, flickering on a reproduced image and sound noise are reduced by frequent switching of antennas.
[0029]
The determination circuit 513 can be said to be a means for evaluating each reception mode. More specifically, the determination circuit 513 stores and holds, as the current best pedestal level, the A / D conversion output value determined to be better than the preset value or the previous A / D conversion output value in the antenna selection process. 521 is compared with the value of the A / D conversion output and the value stored in the bank 521. When the former is equal to or smaller than the latter (the reception level of the currently selected antenna is selected before that) A comparator 522 that generates a latch instruction signal only when it is greater than the reception level of the received antenna, and an A / D conversion output when the latch instruction signal is issued in response to the latch instruction signal from the comparator 522 And a holding unit 523 that takes in the number data of the antenna exhibiting the value as the current best antenna identification information. The holding unit 523 includes a shift register having a 4-bit configuration corresponding to the number of connectable antennas in the antenna switch 1 (see FIG. 1).
[0030]
The bank 521 updates the stored content to the value of the A / D conversion output in response to the latch instruction signal from the comparator 522.
On the other hand, the comparator 522 does not generate a latch instruction signal when the value of the A / D conversion output is larger than the value stored in the bank 521, the bank 521 is not updated, and the holding unit 523 takes in the antenna number. It is not done, so it keeps the contents held so far.
[0031]
Therefore, each time the A / D converter 510 performs the sampling operation, the bank 521 and the holding unit 523 update or hold the best pedestal level so far and the number of the antenna exhibiting the best pedestal level.
The comparator 522 also generates a determination end signal notifying that when the comparison between the value of the A / D conversion output and the value stored in the bank 521 is completed, and supplies the determination end signal to the timing control unit 511. The antenna number data supplied to the holding unit 523 is sent from the antenna switching control circuit 512.
[0032]
The antenna switching control circuit 512 has two 4-bit registers corresponding to antennas. One is antenna correspondence that holds the number data of the antenna that has been confirmed and connected immediately before moving to the antenna selection processing, or the antenna number data that has been confirmed in response to the detection of audio noise described later regardless of the antenna selection processing. The register 524 has a 4-bit configuration, and the other is a shift register 525 that indicates the number of antennas that are sequentially selected and connected in the course of antenna selection processing or the number of antennas that are selectively connected in response to detection of audio noise. is there. The shift register 525 serves as holding means for holding identification information of a receiving antenna to be selected.
[0033]
The antenna switching control circuit 512 also selectively outputs any of the output data of the register 524, the parallel output data of the shift register 525, and predetermined 4-bit data, for example, data of logical value “0000” as shown in the figure. In the antenna selection process based on the output data of the switching circuit 529, the output stage 528 that receives the output data of the switching circuit 529 and generates the antenna switching signals SEL1 to SEL4 according to the switching data, and the output data of the register 524 and the shift register 525 A round detection circuit 526 that detects that the antenna selection has been completed, and output data of the register 524 are transferred in parallel to the shift register 525 only at the time of the first preset, and the contents held in the shift register 525 are forcibly rewritten. 4-bit compatible AND gate group 5 27.
[0034]
Further, the antenna switching control circuit 512 has a 4-bit NAND gate group 520 for forcibly rewriting the contents held in the register 524 by transferring the output data of the shift register 525 in parallel to the register 524 only at the second preset time. .
In response to the antenna update command signal issued from the timing control unit 511, the register 524 can receive the antenna number data from the holding unit 523, and can receive the second preset command signal issued from the timing control unit 511. In response, the output antenna number data of the shift register 525 can be taken in via the NAND gate group 520.
[0035]
Note that the NAND gate group 520 outputs data in which the logic of the output data of the shift register 525 is inverted, but the register 524 has four D flip-flops each having a negative logic preset terminal. Since the output data of the NAND gate group 520 is supplied to the preset terminal, the register 524 is not logically inverted when the second preset command signal is issued. Will be moved to.
[0036]
A first preset command signal from the timing control unit 511 is supplied to one input of the AND gate group 527.
When the round detection circuit 526 detects that the antenna has been selected in the antenna selection process, the round detection circuit 526 supplies a round trip determination signal indicating that to the timing control unit 511.
[0037]
The timing control unit 511 also generates a switching control signal for the switching circuit 529.
Further, the timing control unit 511 supplies a shift command signal to the shift register 525 via the OR circuit 5G1. The shift register 525 shifts the held data in response to the shift command signal, but has a cyclic configuration in which serial output bit data is used as a serial input of the shift register.
[0038]
The shift command signal supplied to the shift register 525 is also generated by a distortion detection signal from the audio distortion detection circuit 3A through the AND circuit 5G2 and the OR circuit 5G1. The output signal of the AND circuit 5G2 is also supplied to a loop detection circuit described later, but a loop detection signal described later is supplied to the AND circuit 5G2 via the NOT circuit 5G3, and the AND circuit 5G2 receives the loop detection signal. Is significantly high, the distortion detection signal is cut off and a low level signal is supplied to the loop detection circuit and OR circuit 5G1.
[0039]
The shift register 525 is also supplied with antenna non-connection information from the antenna switch 1 and takes an operation mode according to this information. The parallel output data of the shift register 525 is sent to the holding unit 523.
The timing control unit 511 is supplied with a 32 fH master clock signal and the QV pulse signal. The antenna selection process is activated by the QV pulse signal, and the control signals of the above-described units at predetermined timings based on the master clock signal Generate a command signal.
[0040]
Each of the registers 523, 524 and 525 has a 4-bit configuration. The antenna number data to be held is "1000" for the antenna ANT1, "0100" for the antenna ANT2, and "0010" for the antenna ANT3. The antenna ANT4 is indicated by “0001”.
Hereinafter, the operation of this circuit will be described in detail.
[0041]
[Antenna selection processing operation]
First, the specific operation of the antenna selection process will be described.
First, as an example of the contents of each register, the antenna connected immediately before the antenna selection process is the antenna ANT1, and data "1000" is stored in the register 524. Assume that a command signal is issued and data “1000” is also stored in the shift register 525. The switching circuit 529 is selected and controlled so as to relay the output data of the register 524 to the output stage 528 before the antenna selection process. It is assumed that an antenna switching signal SEL1 for connection is provided to the antenna switch 1.
[0042]
When a QV pulse is generated in this state, the timing control unit 511 sets a maximum value as an initial value in the bank 521 in response to the rising edge of the QV pulse. Further, immediately after that, the switching circuit 529 is selectively controlled so as to relay the output data of the shift register 525 to the output stage 528. However, here, even if the switching circuit 529 switches the selection from the output data of the register 524 to the output data of the shift register 525, the point that the data “1000” is sent to the output stage 528 does not change, and the antenna ANT1 1 remains electrically connected.
[0043]
Next, as shown in FIG. 5, the timing control unit 511 generates a sampling timing signal that becomes significant at time T1, and the A / D converter 510 captures the pedestal level of the composite video signal at the sampling timing and The A / D conversion output is sent to the determination circuit 513. Here, since the maximum value is set in the bank 521, the comparator 522 determines that the sent A / D conversion output value is smaller than the bank output value, and issues a latch instruction signal. Accordingly, the digital value from the A / D converter 510 is stored in the bank 521 and the output data “1000” of the shift register 525 is taken into the holding unit 523.
[0044]
Thereafter, as shown in FIG. 5, the timing control unit 511 controls the switching circuit 529 to selectively output the data “0000” at time T 2, and all the output stages 528 have the logical value 0 for a predetermined time tm. The antenna switching signals SEL1 to SEL4 are generated. As a result, all electrical connections between the switch 1 and each antenna are released.
[0045]
Subsequent to the release of all the antennas, the timing control unit 511 generates a shift command signal and shifts the data in the shift register 525 by one bit. Then, the content held in the shift register 525 changes from “1000” to “0100”. Then, the timing control unit 511 controls the switching circuit 529 so that the output data of the shift register 525 is selected. Accordingly, since the data “0100” is sent to the output stage 528 via the switching circuit 529, the output stage 528 is an antenna for electrically connecting the antenna ANT2 corresponding to the data “0100”. The switching signal SEL2 is supplied to the switching device 1.
[0046]
When the antenna ANT2 is selected in this way, the timing control unit 511 supplies a sampling timing signal to the A / D converter 510 in order to sample the pedestal level of the composite video signal obtained by the antenna ANT2. The value of the A / D conversion output thus obtained is compared with the value stored in the bank 521 by the comparator 522, and if it is equal or smaller, a latch instruction signal is issued and the value of the A / D conversion output becomes the bank 521. And holding the antenna number data in the holding unit 523. At this time, the data held in the shift register 525 is “0100” corresponding to the antenna ANT2, and the number of the antenna ANT2 is stored in the holding unit 523 as the current best antenna identification information.
[0047]
On the other hand, when the comparator 522 obtains a result that the A / D conversion output value is larger than the bank storage value and the latch instruction signal is not issued, the update of the bank 521 and the update to the holding unit 523 are performed. The antenna number data is not latched, and the already stored pedestal level value of the antenna ANT1 and the number data of the antenna ANT1 remain in the bank 521 and the holding unit 523.
[0048]
After the comparison operation in the determination circuit 513 and the data fetch operation based on the comparison result are completed, the timing control unit 511 controls the switching circuit 529 to selectively output the data “0000”, and again at a predetermined time tm. In the meantime, the output stage 528 generates the antenna switching signals SEL1 to SEL4 all having a logical value of 0 so that each antenna in the switch 1 is released.
[0049]
After the release control of all the antennas, the timing control unit 511 controls the switching circuit 529 so that the output data (“1000”) of the register 524 is selected, and the antenna set immediately before the start of the antenna selection process is performed. Return to the connection of (antenna ANT1 in this example).
In the subsequent processing, the shift operation of the shift register 525, the switching operation of the switching circuit 529, the sampling operation of the A / D converter 510 and the comparison and data acquisition of the determination circuit 513 are performed for the next antenna ANT3 and the next antenna ANT4. Is performed.
[0050]
When the comparison and data fetching operation in the determination circuit 513 for the antenna ANT4 is completed, the bank 521 holds the lowest pedestal level sampled in the antenna selection process, and the holding unit 523 holds the lowest value. The antenna number data exhibiting the pedestal level (good reception level) is stored.
[0051]
As will be described later, in the case of this example, when the antenna ANT4 is selected, a one-round determination signal indicating that selection has been completed for all the installed antennas is issued from the one-round detection circuit 526.
The timing control unit 511 performs an operation of selecting and confirming the best antenna after the round-trip determination signal is generated.
[0052]
That is, as shown in FIG. 5, the timing control unit 511 first performs release control of all antennas in the switch 1 at time T5 as before, and then generates an antenna update command signal. The register 524 takes in the antenna number data stored in the holding unit 523 in response to the antenna update command signal. The timing controller 511 controls the output data of the register 524 to be transferred to the output stage 528 through the switching circuit 529.
[0053]
In this example, if the antenna number data finally stored in the holding unit 523 in the antenna selection process is “0010” corresponding to the antenna ANT3 as shown in FIG. 5, this is transferred to the register 524. Then, the output stage 528 supplies the antenna switching signal SEL3 corresponding to the data "0010" to the switch 1, and the antenna ANT3 is determined by the antenna selection processing. Thereafter, the connection of the antenna ANT3 is continued until a new QV pulse is issued.
[0054]
As the final operation of the antenna selection process, the first preset command signal is supplied to the AND gate 527, the output data of the register 524 indicating the determined antenna number is taken into the shift register 525, and the next antenna selection process is prepared. Made.
It should be noted that the electrical connection of all antennas to the switcher 1 is always released before switching the antennas to be connected, so that simultaneous connection of a plurality of antennas due to delays of circuit elements related to the switching operation is avoided. It is to do.
[0055]
The one-round detection circuit 526 can be composed of four AND gates and one OR gate as shown in FIG.
More specifically, an AND gate 540 that receives the first bit output of the register 524 and the last bit output of the shift register 525, and an AND gate that receives the second bit output of the register 524 and the first bit output of the shift register 525. 541, an AND gate 542 having the third bit output of the register 524 and the second bit output of the shift register 525 as inputs, and an AND having the final bit output of the register 524 and the third bit output of the shift register 525 as inputs. And a four-input OR gate 544 that receives all the outputs of these gates.
[0056]
Therefore, when the antenna selection process is started from a state where, for example, “1000” (antenna ANT1) is stored in the register 524, the data held in the shift register 525 is “0001” (antenna ANT4) by the generation of the shift command signal three times. ), And the last bit output of the shift register 525 exhibits a logical value of 1.
[0057]
The final bit output of the shift register 525 having the logical value 1 is supplied to one input of the AND gate 540, and the other input of the AND gate 540 has a logical value since the register 524 stores “1000” at this time. The first bit output of the corresponding register 524 is supplied. As a result, the AND gate 540 presents an output signal having a logical value of 1, and this becomes a one-round determination output through the OR gate 544. Since the other AND gates 541 to 543 are all given two inputs having a logical value of 0, a signal having a logical value of 1 is not supplied to the OR gate 544 from these gates.
[0058]
As described above, the round-trip determination circuit 526 has the antenna number “0001” (antenna ANT4) which is one before the antenna number “1000” (antenna ANT1) held by the register 524, and the next antenna is the antenna ANT1. When the shift register 525 holds a certain one, a significant one-round determination output (one-round determination signal) is presented.
[0059]
The timing control unit 511 can detect that the evaluation of all the antennas has been completed in the antenna selection process with the one-round determination signal having the logical value 1.
A more specific configuration example of the shift register 525 is shown in FIG.
In FIG. 7, the shift register 525 includes four D flip-flops 530 to 533, output switching type switch circuits 534 to 537 and OR circuits 53 a to 53 d provided corresponding to these D flip-flops.
[0060]
Each of the switch circuits 534 to 537 has one of two output terminals connected to the D input of the corresponding D flip-flop, and the other connected to one input of the corresponding OR circuit.
The other input of the OR circuit is connected to the Q output of the D flip-flop, and the output terminal of the OR circuit is connected to the input terminal of the next switch circuit. However, the output of the final-stage OR circuit 53d is connected to the input terminal of the first-stage switch circuit 534, thereby realizing a circulation type configuration.
[0061]
An antenna non-connection information signal is supplied to the control ends of the switch circuits 534 to 537. The outputs of the OR circuits 53a to 53d are derived as parallel output data of the shift register 525.
According to such a configuration of the shift register 525, even if there is an antenna that is not coupled (not used) to the switch 1, the number of register stages is changed according to the antenna non-connection information signal. Processing is performed.
[0062]
For example, when the antenna ANT2 is not used, a control signal indicating that fact is supplied to the switch circuit 535, and only the switch circuit 535 receives the input signal via the corresponding OR circuit 53b and the switch circuit 536 in the next stage. To be transmitted to the input. As a result, the data after “1000” does not become “0100” but can be changed to “0010”, and the processing relating to the antenna ANT2 can be skipped to perform the antenna selection processing and the audio noise response processing described later. it can.
[0063]
As can be seen from the above description, when the antenna selection process is executed when the antenna ANT1 is selected before the QV pulse is generated and the antenna ANT3 is finally selected, ANT1 → ANT2 → ANT1 → ANT3 → ANT1 → The antenna is switched in the manner of ANT4 → ANT1 → ANT3. This is also shown in FIG.
Unlike this case, for example, as shown in (1) of FIG. 8, when the antenna selection process is executed from the state in which the antenna ANT3 is selected before the QV pulse is generated and the antenna ANT2 is finally selected, for example. The antenna is switched in the following manner: ANT3 → ANT4 → ANT3 → ANT1 → ANT3 → ANT2 → ANT3 → ANT2. In other words, in this embodiment, the antenna selected immediately before the start of the antenna selection process is the first antenna to be selected in the antenna selection process (first antenna for reception level sampling), and this antenna is selected in order from the first selected antenna. It is going to be selected. As a result, the antenna is not switched for sampling the pedestal level at the beginning of the antenna selection process, and the overall noise generation period tn associated with the antenna switching can be shortened.
[0064]
On the other hand, when the antenna selected first in the antenna selection process is fixed, for example, when the fixed antenna is ANT1, as shown in FIG. 8 (2), ANT3 → ANT1 → ANT3 → ANT2 → The antenna is switched in a manner of ANT3 → ANT4 → ANT3 → ANT2. Therefore, in this case, unless the fixed antenna ANT1 is selected before the QV pulse is generated, the antenna is always switched immediately after the start of the antenna selection process. Accordingly, as shown in FIG. 8 (2), the overall noise generation period tn 'associated with antenna switching becomes longer than in the case of (1) above.
[0065]
Thus, since the antenna selection process in the present embodiment can take the aspect (1) above, the audio noise generation period in the antenna selection process can be suppressed as much as possible.
Note that time T1 to time T5 shown in FIG. 8 correspond to time T1 to time T5 shown in FIG. 5, respectively, and the processing associated with time T1 to time T4 is antenna switching processing and level detection (holding). It corresponds to processing. Further, the process associated with time T5 corresponds to an antenna determination process. As described above, the antenna selection process is classified into an antenna switching process, a level detection (holding) process, and an antenna determination process, and can be said to include these processes.
[0066]
[Voice noise response processing operation]
Before describing the operation of the audio noise response process in the configuration of FIG. 4, the audio distortion detection circuit 3A that generates the distortion detection signal supplied to the AND circuit 5G2 will be described in detail.
FIG. 9 shows a specific configuration of the distortion detection circuit 3A.
[0067]
In FIG. 9, a band pass filter (BPF) 3A1 to which a composite audio signal obtained from the FM detection circuit 32 is supplied is provided as a preceding stage of the distortion detection circuit 3A. The characteristics of this BPF 3A1 are set so as to pass the harmonic component of the subcarrier in the received composite signal. For example, fourth to sixth harmonics can be used.
[0068]
The signal that has passed through the BPF 3A1 is supplied to the amplitude detection circuit 3A2, where so-called AM demodulation is performed, and the demodulated output is supplied to the differentiation circuit 3A3. The differentiation circuit 3A3 extracts the rising component of the demodulated output waveform and supplies the extracted component to one input terminal of the comparator 3A4. A sensitivity adjustment signal is supplied to the other input terminal of the comparator 3A4, and a comparison reference voltage VR of a level corresponding to the signal is set.
[0069]
The comparator 3A4 generates a distortion detection signal that becomes a high level only when the level of the signal from the differentiation circuit 3A3 is larger than the reference voltage VR. Therefore, the distortion detection signal is a signal that bears two levels of high and low. This distortion detection signal is output in synchronization with the 32 fH clock signal by the D flip-flop 3A5.
[0070]
In such a configuration, the differentiating circuit 3A3 detects a rise of the distortion component of the audio signal, that is, a sudden increase change of the distortion component of the audio signal, so that the distortion can be detected without delay. In addition, a distortion detection signal that does not react to continuous noise such as inter-station noise can be obtained.
The distortion detection signal thus obtained is supplied to the AND circuit 5G2, and becomes a shift command signal to the shift register 525 through the AND circuit 5G2 and the OR circuit 5G1 while the loop detection signal described later is at a low level.
[0071]
The shift command signal based on the distortion detection signal activates the antenna switching process in response to a large distortion of the audio signal that may occur at any time, unlike the antenna selection process executed for each field described above. In the antenna switching control circuit 512 shown in FIG. 4, by using such a shift command signal, an operation of switching to the antenna of the next number of the antenna electrically connected to the current switch 1 is guided.
[0072]
That is, when a shift command signal based on the distortion detection signal is generated, the shift register 525 shifts the held data by one bit. For example, when the selected antenna is the antenna ANT1 and the data held in the shift register 525 is “1000”, if a distortion detection signal is generated because the audio signal is distorted due to the deterioration of the reception state, the shift register 525 The retained data is “0100”. If a distortion detection signal is generated again, the data held in the shift register 525 further advances to “0010”.
[0073]
The timing control unit 511 generates a second preset command signal each time the data held in the shift register 525 is changed (shifted), and causes the NAND circuit 520 to transfer the data held in the shift register 525 to the register 524. Let them control. In addition, at least immediately after the data transfer from the shift register 525 to the register 524 is completed, the timing control unit 511 controls the switching circuit 529 to send the data in the register 524 to the output stage 528.
[0074]
Therefore, in this example, in response to the distortion detection signal, the electrical connection of the antenna to the switch 1 is switched in the order of ANT 1 → ANT 2 → ANT 3 → ANT 4 → ANT 1.
If the reception state by the antenna ANT3 is good after the switching to the antenna ANT3 and the distortion detection signal is not generated, the data held in the shift register 525 and the register 524 is not changed, and the electrical connection to the switch 1 of the antenna ANT3 is not changed. Maintained. However, since the antenna selection process described above is executed by the subsequent generation of the QV pulse, the connection of the antenna ANT3 is released.
[0075]
The antenna selected according to the sound distortion may be different from the antenna determined by the previous antenna selection process. Therefore, the antenna selection process is started from the initial state where the number data of the antenna selected by the audio distortion (number data of the antenna ANT3 in this example) is held in the register 524 and the shift register 525.
[0076]
Note that the voice response processing operation described here also deals with the unconnected antenna described in FIG.
[0077]
[Video Diversity / Audio Diversity]
The first diversity by the antenna selection process is started by the QV pulse based on the vertical synchronization timing to optimize the quality of the reproduced image, and is performed for each field which is a unit of video carried by the composite video signal. Therefore, this diversity can be said to be a diversity synchronized with the reproduced video (hereinafter referred to as video diversity).
[0078]
On the other hand, the second diversity by the sound noise response process is activated every time the reproduced sound is distorted to optimize the quality of the reproduced sound. That is, this is performed at any time regardless of the field without periodicity like video diversity. Therefore, this diversity can be said to be diversity in response to the deterioration of the reproduced voice (hereinafter referred to as voice diversity).
[0079]
When these two types of video diversity and audio diversity are simply combined, if a QV pulse is generated immediately after switching the antenna due to audio diversity and a QV pulse is generated, a good antenna for the reproduced video selected in the video diversity May be different from the antenna selected for voice diversity. For example, it is conceivable that the antenna ANT3 is finally selected in the video diversity after the antenna ANT1 is selected in the audio diversity, and then the audio diversity is performed in a short time and the antenna ANT1 is selected again. This will not effectively eliminate multipaths that affect the voice.
[0080]
Therefore, in this embodiment, a mode is adopted in which the operation of video diversity is limited after the antenna is switched by audio diversity. More specifically, immediately after the antenna switching by the distortion detection signal as the audio system trigger, the video diversity operation based on the vertical synchronization detection, that is, the QV pulse is prohibited.
[0081]
An example of a diversity matching circuit for realizing this is shown in FIG.
In FIG. 10, the diversity matching circuit includes a D flip-flop 701 having a QV pulse as a trigger input and a high level signal as a D input. The Q output of the D flip-flop 701 is supplied to the D input of the next stage D flip-flop 702. The inversion signal of the QV pulse from the NOT circuit 70N is supplied to the trigger input of the D flip-flop 702, and the Q output signal is supplied to one input of the AND circuit 703.
[0082]
Each of the D flip-flops 701 and 702 is supplied with a distortion detection signal from the audio distortion detection circuit 3A as a reset input. A QV pulse is supplied to the other input of the AND circuit 703. A QV2 pulse as a modified QV pulse is emitted from the output of the AND circuit 703. The QV2 pulse is used in place of the QV pulse used in each circuit described so far.
[0083]
FIG. 11 shows an operation waveform of each part of the diversity matching circuit having such a configuration.
In FIG. 11, in a situation where the audio distortion detection signal is not significant, that is, does not become a high level, the D flip-flop 701 is triggered and set at the rise of the QV pulse, and the D flip-flop 702 is triggered at the fall of the QV pulse. Is set. While the D flip-flop 702 is in the set state, the gate of the AND circuit 703 is opened, so that the QV pulse is output as it is as the QV2 pulse.
[0084]
On the other hand, when the audio distortion detection signal becomes a high level, the D flip-flops 701 and 702 are forcibly reset, so that the gate of the AND circuit 703 is closed and the output of the QV pulse is blocked (masked). Is done. As a result, the QV2 pulse that should be generated following the distortion detection signal is not generated, and the video diversity operation is prohibited, and the audio diversity operation in response to the distortion detection signal is performed.
[0085]
However, since the D flip-flops 701 and 702 are sequentially set again by the QV pulse immediately after generation of the distortion detection signal, it is allowed to output the QV pulse as it is as the QV2 pulse.
Since the period of the QV pulse is about 16.6 msec corresponding to one field, the period in which the video diversity is prohibited in the present embodiment is about 16.3 m after the generation of the audio distortion detection signal, that is, after the antenna switching by the audio diversity. Video diversity is prohibited during the period from 6 msec to 33 msec. During this period, audio-oriented playback with reduced influence of, for example, multibus, which causes audio distortion, is performed.
[0086]
In this embodiment, it is considered that it is practically sufficient to prohibit video diversity over a period of about 16.6 msec to 33 msec after execution of audio diversity, and only one video diversity operation immediately after execution of audio diversity is performed. However, if necessary, the video diversity for two times after the voice diversity is executed may be prohibited, or a longer prohibition period may be provided.
[0087]
[Loop detection]
As described above, when two functions of audio diversity and video diversity are provided, when antennas that are opposite to each other are selected for audio diversity and video diversity, two different antennas continue to be alternately repeated (hereinafter referred to as a loop). Occurs).
[0088]
For example, when the antenna ANT1 is selected by video diversity and the antenna ANT2 is selected by voice diversity, the antenna is selected in the order of ANT1, ANT2, ANT1, ANT2, and so on. As a result, a state in which noise is periodically generated in both the reproduced video and the reproduced audio is continued.
[0089]
This is shown in FIG.
In FIG. 12, m represents the number of the antenna selected by video diversity, and m + 1 represents the number of the antenna selected by voice diversity (here, an example in which antenna switching has been performed once by voice diversity) is given. ).
[0090]
In this embodiment, the occurrence of such a loop is detected, and control for breaking the loop is performed. More specifically, when the loop is detected, audio diversity is prohibited for a certain period of time, and only the quality of the reproduced video is pursued.
FIG. 13 shows a configuration example of the loop detection circuit.
In FIG. 13, the loop detection circuit 5X0 uses four output data of the holding unit 523 as D inputs and is triggered by an antenna update command signal (same as that supplied to the register 524) from the timing control unit 511. It has the 2nd holding | maintenance part 5X which consists of D flip-flops.
[0091]
The loop detection circuit 5X0 also corresponds to each D flip-flop in the second holding unit 5X, and the EXOR circuit group 5X1 and the EXOR circuit group 5X1 that receive the output data of the holding unit 523 and the Q output signal of the D flip-flop 5X, respectively. And a four-input NOR circuit 5X2 that receives each of the outputs.
Furthermore, the loop detection circuit 5X0 inverts the output signal of the AND circuit 5X9, the NOT circuit 5X8 that inverts the antenna update command signal, the AND circuit 5X9 that has the inverted output as one input and the negative logic clear signal CLR as the other input. The D flip-flop 5X5, which uses the high-level signal as the D input and the output signal of the gate 5G2 (see FIG. 4) as the trigger input, and the output signal of the NOR circuit 5X2 as one input and the Q output signal of the D flip-flop 5X5 as the reset input The AND circuit 5X6 as another input, the first stage D flip-flop 5X3 using the output signal of the AND circuit 5X6 as a D input and the loop detection timing signal generated from the timing control unit 511 as a trigger input, and the output signal D of the NOR circuit 5X2 Q output signal of flip-flop 5X3 and D flip-flop 5 5 of the Q output signal has a 3-input AND circuit 5x7 which inputs respectively, and a rear stage D flip-flop 5X4 to the output signal of the AND circuit 5x7 D type trigger input loop detection timing signal.
[0092]
A loop detection signal that is significant at a high level is generated from the Q output of the D flip-flop 5X4, and is supplied to the AND circuit 5G2 (both see FIG. 4) via the NOT circuit 5G3.
The loop detection circuit 5X0 detects that the same antenna has been continuously selected a predetermined number of times by video diversity with an antenna selection operation by audio diversity in between, and generates a high-level loop detection signal.
[0093]
The second holding unit 5X is similarly updated at the timing when the register 524 in the antenna switching control circuit 512 is updated to the antenna number data transferred from the holding unit 523 in the determination circuit 513. That is, as described above, the holding unit 523 holds the number data of the antenna having the highest evaluation in the antenna selection process at the end of the antenna selection process, and the second holding unit 5X stores the same number data Capture at the end of the antenna selection process.
[0094]
As a result, even if audio diversity is performed after one antenna selection process as video diversity or the content of the holding unit 523 changes due to the next antenna selection process, the antenna number data selected and confirmed in the one antenna selection process Can be held in the second holding portion 5X. More specifically, even when the shift command signal based on the audio distortion detection signal shifts the data held in the shift register 525 and the second preset command signal takes the shifted data into the register 524, the holding unit 523 and the second The content of the holding unit 5X does not change. Even if the antenna selection process is newly started, the contents of the holding unit 523 are changed, but the antenna number data selected and confirmed in the previous antenna selection process is used until the antenna update command signal is issued. It is possible to hold it.
[0095]
For example, if the holding unit 523 holds “1000” at the end of the antenna selection process, “1000” is set to both the register 524 and the shift register 525 and the second holding unit 5X by the response operation to the antenna update command signal. Is stored. Thereafter, when a shift command signal based on the audio distortion detection signal is issued, the registers 524 and 525 shift to “0100”, but the data held in the second holding unit 5X remains “1000”.
[0096]
The data held in the second holding unit 5X is detected for each bit in the EXOR circuit group 5X1 with the data held in the holding unit 523, and the NOR circuit 5X2 determines whether all the bits match. That is, the holding data of the holding unit 523 is the antenna number data evaluated and determined to be the best by the current antenna selection process, and the holding data of the second holding unit 5X is the previous antenna selection process. Therefore, a match / mismatch determination of both data is made.
[0097]
The appropriate timing of the coincidence / non-coincidence determination can be the timing immediately before the antenna update command is issued to the second holding unit 5X. Strictly speaking, the holding unit 523 has the best antenna number in the current antenna selection process. This corresponds to a period from the time when the data is determined to the time immediately before the antenna update command is issued. At a predetermined timing during such a period, the timing control unit 511 generates a loop detection timing signal.
[0098]
On the other hand, the D flip-flop 5X5 is usually reset in response to the generation of the antenna update command signal except when the clear signal CLR is generated as a global reset (so-called power-on reset or the like), and the distortion is detected through the gate 5G2. A trigger is applied by the signal and a set state is set. That is, the D flip-flop 5X5 is reset after the end of the antenna selection process by the antenna update command signal generated every time the antenna selection process ends, and is set by the distortion detection signal generated after the reset. In other words, the D flip-flop 5X5 detects the generation of the distortion detection signal after the end of the antenna selection process, and is set only when the generation is detected, and outputs the high-level Q output signal to the other input of the AND circuit 5X6. To supply.
[0099]
Therefore, the AND circuit 5X6, based on the low / high level output of the NOR circuit 5X2 that bears the match / mismatch determination result and the Q output of the D flip-flop 5X5, determines the best antenna number (for example, M) and the best antenna number determined by the current antenna selection process coincide with each other, and an output signal that becomes a high level is generated only when a distortion detection signal is generated after the previous antenna selection process is completed. That is, the AND circuit 5X6 detects that the antenna number has changed from (m) → (m + 1) → (m) (first mode) and generates a high level signal.
[0100]
If the previous antenna number and the current antenna number do not match and the transition is, for example, (m) → (m + 1) → (m + 2), the NOR circuit 5X2 does not issue a match determination output (low level output). In addition, even if the previous antenna number and the current antenna number match, no distortion detection signal has been generated after the previous antenna selection process has ended, and for example, a transition such as (m) → (m) has occurred. Then, since the D flip-flop 5X5 that is not triggered in the reset state generates a low-level Q output, a low-level signal is generated from the AND circuit 5X6.
[0101]
Since the D flip-flop 5X3 is triggered by the loop detection timing signal as described above, the high / low level signal corresponding to the first mode or the non-first mode is captured and held.
In the AND circuit 5X7, information indicating whether or not the first mode is held in the D flip-flop 5X3, previous and current determined antenna number match / mismatch determination output information from the NOR circuit 5X2, and D flip-flop 5X5 The generation / non-occurrence information of the distortion detection signal after the previous antenna selection processing by the Q output is supplied. Therefore, the AND circuit 5X7 outputs a high level signal only when the previous and current confirmed antenna numbers coincide with the first mode and a distortion detection signal is generated after the previous antenna selection process. In other words, the AND circuit 5X7 generates a full match of the determined antenna numbers by the three consecutive antenna selection processes from the previous time, generates a distortion detection signal after the previous antenna selection process, and generates a distortion detection signal after the previous antenna selection process. Generates a high level signal by detecting that the antenna number has changed from (m) → (m + 1) → (m) → (m + 1) → (m) (second mode), for example. To do.
[0102]
The high level signal from the AND circuit 5X7 according to the second aspect is taken in response to the loop detection timing signal in the D flip-flop 5X4 and becomes a high level loop detection signal.
As shown in FIG. 4, the high-level loop detection signal closes the gate of the AND circuit 5G2 via the NOT circuit 5G3 to block the transmission of the distortion detection signal. As a result, a voice diversity prohibited state in which a shift command signal to the shift register 525 by the distortion detection signal cannot be issued.
[0103]
Since the loop detection timing signal is issued prior to the antenna update command signal and has a period of one field, the voice diversity prohibition state is continued or released in units of one field. In other words, the voice diversity prohibition state continues for a period corresponding to at least one field.
[0104]
When the second mode cannot be determined, the D flip-flop 5X4 generates a low-level loop detection signal, so that the gate of the AND circuit 5G2 is opened and the distortion detection signal can be transmitted to the shift register 525. The voice diversity prohibition state is canceled.
Here, the unit of the duration of the voice diversity prohibition state is a period corresponding to one field. However, the unit is not limited to this, and the unit can be appropriately determined.
[0105]
In FIG. 13, the clear signal CLR has been described so as to reset only the D flip-flop 5X5. However, such a clear signal is not limited to each flip-flop of the second holding unit 5X, but also the D flip-flop 5X3. And 5 × 4 initial reset signal.
[0106]
[Modification]
In addition to the aspects described above, the following modifications can be made to perform finer diversity control.
Firstly, an aspect is introduced in which the sensitivity of the audio system is suppressed so that video is emphasized when the reception state deteriorates.
[0107]
This is achieved by changing the reference voltage VR of the comparison circuit 3A4 in the audio distortion detection circuit 3A shown in FIG. 9 or changing the gain of the differentiation circuit 3A3 when the deterioration of the reception state is detected. be able to.
Secondly, when there are subcarriers (corresponding to stereo broadcasting or bilingual broadcasting) in the audio composite signal, a mode of increasing the sensitivity of the audio system or a mode of enabling the audio system only at this time is derived. These deal with the fact that subcarriers are susceptible to multipath.
[0108]
Third, when an externally input video such as navigation is output, there are a mode in which the video system is disabled, and a mode in which the sensitivity of the audio system is increased together with or in place of this mode.
The mode of disabling the video system can be achieved by providing a gate for limiting output to the subsequent stage of the QV pulse.
[0109]
Also, as a method for invalidating the audio system, as can be understood from the above description, a gate for limiting output to the subsequent stage of the distortion detection signal may be used.
Next, the clamp circuit 40 and its control mode in this embodiment will be described.
FIG. 14 shows a configuration example of the clamp circuit 40, and the output signal of the AM detection circuit 22 is supplied to the gate of the n-channel MOS transistor 404 via the clamp capacitor 408. The drain of the n-channel MOS transistor 401 is connected to the connection line between the capacitor 408 and the MOS transistor 404, and the power supply line is connected to the source of the MOS transistor 401.
[0110]
A connection line between the capacitor 408 and the MOS transistor 404 is also led to the output terminal. Further, this connection line is grounded via a constant current source 409.
The gate of n channel MOS transistor 401 is connected to the source of n channel MOS transistor 406. The MOS transistor 406 is supplied with an antenna switching signal at its gate and grounded at its source. This antenna switching signal is generated from the control unit 5 and becomes significant at the timing of switching the antenna in the antenna selection processing, strictly speaking, at the timing corresponding to the middle of switching of the antenna.
[0111]
The MOS transistor 404 and the n-channel MOS transistor 405 form a pair with the MOS transistor 405 and play a main part of the balanced differential amplifier circuit.
The sources of the MOS transistors 404 and 405 are commonly connected, and the common connection line is grounded via a constant current source 407. The clamp voltage Vc generated by the voltage source 410 is supplied to the gate of the MOS transistor 405. The drain of the MOS transistor 404 is supplied with power through the p-channel MOS transistor 402. In contrast, the drain of the MOS transistor 405 is also supplied with power through the p-channel MOS transistor 403. The gates of the MOS transistor 402 and the MOS transistor 403 are connected to each other, and this connection line is connected to the source of the MOS transistor 405.
[0112]
The drain of the MOS transistor 404 is derived as an output of the differential amplifier circuit and is connected to the gate of the MOS transistor 401.
The clamp circuit 40 having such a configuration has a main feature in the configuration of an n-channel MOS transistor 406 that is supplied with an antenna switching signal and controls the MOS transistor 401 in response thereto.
[0113]
The clamp circuit 40 operates so as to maintain the sync chip potential in the input composite video signal at the clamp voltage Vc.
More specifically, when the input is lower than the clamp voltage Vc, a signal corresponding to this is supplied to the gate of the MOS transistor 401, the transistor 401 is turned on, and a current flows into the clamp capacitor 408. Conversely, when the input is higher than the clamp voltage Vc, the MOS transistor 401 is turned off, and current flows out from the capacitor 408 via the constant current source 409.
[0114]
By continuously performing such clamp control for supplying and sinking current to the capacitor 408, the sync chip potential of the input composite video signal is maintained at the clamp voltage Vc.
The MOS transistor 406 is provided so that such clamp control can be temporarily stopped. The purpose of this temporary stop is to suppress an adverse effect on the synchronization separation processing in the waveform shaping circuit 41 when the reception level of the switched antenna is good. In other words, the circuit portion excluding the MOS transistor 406 and its connection corresponds to clamping means for keeping the DC potential of the sink chip constant, and the MOS transistor 406 has a function of disabling the clamping means.
[0115]
That is, when the antenna switched for confirmation (evaluation) of the reception level in the antenna selection process as described above shows a better reception level than the antenna set up to that point, the sync chip in the composite video signal during antenna switching The level will be lower than that before switching. When clamp control is performed following the movement of this potential, a current flows from the MOS transistor 401 to the capacitor 408 and the potential of the capacitor 408 increases. Then, when switching to the original antenna again, the potential of the sync chip may reach a level exceeding the threshold level of the comparator 83 for synchronization separation arranged in the subsequent stage of the waveform shaping circuit 41. Accurate sync separation cannot be performed. (See Figure 15)
Therefore, in this embodiment, the MOS transistor 406 is controlled so as to stop the clamp control while the antenna is being switched.
[0116]
Specifically, a gate control signal indicating a high level is input to the MOS transistor 406 during antenna switching. In response to this gate control signal, the MOS transistor 406 is turned on and the MOS transistor 401 is turned off.
When the MOS transistor 401 is turned off, no current flows to the capacitor 408, so that an increase in the sink chip potential exceeding the threshold level as described above can be suppressed, and as a result, more accurate synchronous separation is possible. is there. (See Figure 16)
By achieving accurate synchronization separation in this way, the processing for the diversity operation described so far can be surely executed.
[0117]
In the above embodiment, the spatial diversity operation is described in which the reception mode is changed by switching the reception antenna based on the level detection of the composite video signal. However, the optimum reception mode is changed by changing the reception mode by another method. You may apply to the diversity operation to select.
In the above embodiment, the configuration corresponding to the television signal of the NTSC system has been described. However, the present invention can also be applied to the configuration corresponding to the television signal of another format.
[0118]
In addition to the above, various means have been described in a limited manner in the above embodiment, but can be appropriately modified within a range that can be designed by those skilled in the art.
[0119]
【The invention's effect】
As described above in detail, according to the present invention, it is possible to provide a television receiver capable of performing an optimal diversity operation in terms of quality with respect to an actual viewer of reproduction information including sound.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a schematic configuration of a diversity television receiver according to an embodiment of the present invention.
2 is a block diagram showing a configuration of a QV pulse generation circuit in the receiver of FIG. 1. FIG.
FIG. 3 is a time chart showing the operation of the QV pulse generation circuit of FIG. 2;
4 is a block diagram showing a configuration of an antenna selection processing circuit formed in a control unit in the receiver of FIG. 1. FIG.
FIG. 5 is a time chart showing an operation in video diversity of the antenna selection processing circuit of FIG. 4;
6 is a block diagram illustrating a configuration example of a circuit determination circuit in the antenna selection circuit of FIG. 4;
7 is a block diagram showing a configuration of an antenna switching register in the antenna selection processing circuit of FIG. 4;
FIG. 8 is a time chart showing a characteristic operation of antenna selection processing in the present embodiment.
9 is a block diagram showing a specific configuration example of an audio distortion detection circuit in the receiver of FIG. 1. FIG.
10 is a block diagram showing a specific configuration example of a diversity matching circuit in the receiver of FIG. 1. FIG.
11 is a time chart showing the operation of the diversity matching circuit of FIG.
FIG. 12 is a diagram for explaining a loop phenomenon of antenna selection that may occur when video diversity and audio diversity are combined.
13 is a block diagram illustrating a specific configuration example of a loop detection circuit in the receiver of FIG. 1. FIG.
14 is a block diagram illustrating a specific configuration example of a clamp circuit in the receiver of FIG. 1. FIG.
FIG. 15 is a time chart for explaining a defect of the clamp circuit.
16 is a time chart showing a characteristic operation of the clamp circuit of FIG. 18;
[Explanation of symbols]
ANT1-ANT2 receiving antenna
1 switch
2 Video signal playback system
21 Video intermediate frequency amplifier
22 AM detector circuit
2x CRT
3 Audio signal playback system
31 Audio intermediate frequency amplifier
32 FM detector circuit
3A distortion detection circuit
3x speaker
40 Clamp circuit
41 Waveform shaping circuit
5 Control unit
60 LPF
61 Phase comparator
62 LPF
63 VCO
64 divider circuit
65 Clock generation circuit
81 Inversion circuit
82 LPF
83 level comparator
50 QV pulse generation circuit
500-503 D flip-flop
505, 506 NOT circuit
504 AND circuit
509 D flip-flop group
510 A / D converter
511 Timing control unit
513 judgment circuit
512 Antenna switching control circuit
521 Bank
522 Comparator
523 holding part
524 registers
527 AND circuit group
526 round-trip determination circuit
525 shift register
529 switch circuit
528 output stage
520 NAND circuit group
5G1 OR circuit
5G2 AND circuit
5G3 NOT circuit
540-543 AND circuit
544 OR circuit
534-537 switch circuit
530-533 D flip-flop
53a-53d OR circuit
3A1 BPF
3A2 amplitude detection circuit
3A3 Differentiation circuit
3A4 comparator
5A5 D flip-flop
701,702 D flip-flop
70N NOT circuit
703 AND circuit
5X0 loop detection circuit
5X second holding part
5X1 EXOR circuit group
5X2 NOR circuit
5X3, 5X4, 5X5 D flip-flop
5X7, 5X9 AND circuit
5X8 NOT circuit
401, 404, 405, 406 n-channel MOS transistor
402,403 p-channel MOS transistor
409, 407 constant current source
410 constant voltage source

Claims (7)

A television receiver that performs a diversity operation according to a reception state, a demodulating unit that demodulates a composite video signal and an audio signal from a received signal, and a vertical timing detecting unit that detects a timing of a vertical synchronizing signal in the composite video signal And a distortion detection unit that determines that the distortion of the audio signal has exceeded a predetermined level and generates a distortion detection signal, and performs a video diversity operation based on the timing detected by the vertical timing detection unit, Control means for executing an audio diversity operation in response to the distortion detection signal, and the control means prohibits the video diversity operation for a predetermined period after the distortion detection signal is issued. A featured television receiver. The system further comprises loop detection means for detecting a state in which the reception modes that are opposite to each other in the video diversity operation and the audio diversity operation are selected and continuously repeating the reception mode as a loop, and the control means includes the loop television receiver according to claim 1 Symbol placement and inhibits the sound diversity operation when it is detected. It said distortion detection means includes a differentiating means for detecting a steep increase change in the distortion components of the audio signal, the claim 1, characterized in that for generating the distortion detection signal based on the differential output of the differentiating means, or 2. The television receiver according to 2 . The distortion detection means includes a band-pass filter to which the audio signal is supplied, an amplitude detection circuit to which an output signal of the band-pass filter is supplied, and a differentiation circuit that extracts a rising component of an output signal waveform of the amplitude detection circuit And a comparator that compares the extracted component level of the differentiating circuit with a reference value and generates a distortion detection signal that is significant when the extracted component level is greater than the reference value. The television receiver according to any one of claims 1 to 3 . The video and audio diversity operation, any one of claims 1 to 4, wherein the the operation of the spatial diversity taking alteration of the reception mode by which to select any of the plurality of receiving antennas The television receiver as described in any one. Has a holding means for holding identification information of the receiving antenna to be selected, said control means, claims 1, characterized in that allowed to change in response to contents held in said holding means to the distortion detection signal 5, wherein The television receiver according to any one of the above. 7. The television receiver according to claim 6 , wherein, in the video diversity operation, evaluation of the reception mode is started from the reception mode by the reception antenna corresponding to the identification information held in the holding means.

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