JPS60150395A - Reproducing video signal processing circuit - Google Patents

Abstract

PURPOSE:To save one 1H delay line in comparison with a conventional device by adopting the constitution that a 1H delay circuit used for dropout compensation circuit and a high frequency noise reduction circuit in a luminance signal system and a 1H delay circuit used for a comb line filter in a chrominance carrier signal system in common so as to use two 1H delay lines. CONSTITUTION:When a dropout is caused, a switch 7 is thrown to the position of a terminal (b), and an output of an equalizer 37 is extracted while being replaced with a signal before 1H from a 1H delay circuit 35 and a low pass filter 36. On the other hand, an output of the 1H delay circuit 35 is delayed by 1H further at a 1H delay circuit 38, a luminance signal component is eliminated at a band pass filter 39 and the result is fed to an adder 40 in opposite phase. The output of an adder 34 is fed to an adder 40 while the luminance signal component is eliminated at a band pass filter 41 while equal delay amount as that of the band pass filter 39. A 2H delay comb line filter is constituted by the 1H delay circuits 35, 38, the band pass filters 39, 41 and the adder 40 so as to eliminate crosstalk disturbance.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a reproduced video signal processing circuit, in which a reproduced luminance signal is extracted through a dropout compensation circuit, and a reproduced carrier color signal is extracted through a comb filter. The present invention relates to a reproduced video signal processing circuit.

PRIOR ART FIG. 1 shows a block diagram of an example of a conventional reproduction video signal processing circuit of the PΔ1 type. In the figure, the video signal Tq generated by the magnetic heads 1a and Ib is sent to the preamplifier 2.
After being amplified by a and 2b, the signal is supplied to a high-pass filter 4 via a switch 3 which is switched by a drum pulse, and is converted into a luminance 1α signal, while the signal is supplied to a low-pass filter 5, and the m
It is considered to be a fading signal.

No. 43 taken out from the high-pass filter 4 is connected to the switch 7.11 which is connected to the dropper 1 to the detector 61 normal state a and to the dropper 1 to the detection terminal 1.
” Dropout compensation circuit 9 composed of delay circuit 8
Normally, it is taken out as is, but when detecting drop alarm 1, it is replaced with the signal before 11-1 and supplemented to drop alarm 1, and the FM demodulator 10 outputs F
After M demodulation, unnecessary frequency components are removed by a low-pass filter 11 and the signal is supplied to a high-frequency noise reduction circuit 12. In the high frequency noise reduction circuit 12, the output of the 11-1 delay circuit 8 is transmitted to the FM demodulator 13. The output of the adder 15 is added to the output of the low-pass filter 11 in reverse phase through the low-pass filter 14 in an adder 15, and the output of the adder 15 is amplitude-limited by a limiter 16 and added to the output of the low-pass filter 11 in reverse phase. The sum is added in the container 17 and taken out. Thereby, under normal conditions, the luminance signal is extracted with high-frequency noise components reduced.

On the other hand, the signal taken out from the low-pass filter 5 is frequency-converted by a frequency converter 18, and unnecessary frequency components are removed by a band-pass filter 19, resulting in 2H! 1 extension circuit 20. In the adder 21, crosstalk interference from adjacent tracks is removed by the comb filter 22 formed by IJn, and the signal is supplied to the adder 23 and the APC circuit 2/'I.

The output of the comb filter 22 is burst goo 1 to circuit 25.
The phase comparison error signal is supplied to a phase comparator 27 along with the output of the standard oscillator 26 for phase comparison, and the phase comparison error signal is supplied to a voltage controlled oscillator 28 to control its output oscillation frequency. The output of the voltage controlled oscillator 28 is phase-shifted by 90° in a phase shifter 29 and supplied to a frequency converter 30, where it is output to an oscillator 31.
The frequency is converted by the signal from the bandpass filter 32.
The signal is supplied to the frequency converter 18 via the converter 18, where the frequency is converted.

Output of comb filter 22 and high frequency noise reduction circuit 12
The output of r: IJn CN is sent to the adder 23 and taken out from the output terminal 33.

However, in the conventional circuit mentioned above, the 114 delay circuit 8 and the 2-day delay circuit 20 are used separately for the luminance signal system and the carrier color signal system. One delay line (generally a glass delay line is used) requires a total of three, and there was a problem that the circuit could not be easily constructed.

Means for Solving the Problems The present invention provides means for adding the reproduced luminance signal and the reproduced carrier color signal, and uses a comb filter to add the output of the means to 11''.
Or, 1j11 is formed using a delay circuit that delays by 2 days and a filter that removes and covers the luminance signal component from the output of this delay circuit,
A dropout compensation circuit, a filter for removing the carrier color signal component from the output of the Chikanobu circuit and the delay circuit, and a switch for switching between the output of the carrier color signal component removal filter and the reproduced luminance signal g. The above-mentioned problems have been solved by constructing the device, and each embodiment thereof will be described with reference to FIG. 2 and subsequent figures.

Embodiment 112 FIG. 112 shows a block system diagram of a first embodiment of the circuit of the present invention. In the figure, the same components as those in FIG. In the figure, the output of the low-pass filter 11 and the output of the bandpass filter 19 are
/l, and the 11-1 delay circuit 35 adds 11-1
After being delayed, the carrier color signal component is removed by a low-pass filter 36 (delay L14Δα), and the signal is supplied to the adder 15 in reverse phase, while being supplied to the switch 7.

The output of the low-pass filter 11 is sent to the equalizer 37 to correct the stored extension Δα caused by the low-pass filter 36, and then sent to the tightener 15.
17. Here, the output of the low-pass filter 3G is supplied to the adder 15 in reverse phase, and after being multiplied with the output of C i = + Li → J It is added to the output of the equalizer 37.

When drop error 1~ is occurring, switch 7 is set to 9.
;::Connected to a, the output of the equalizer 37 is 11.
delay circuit 35, low-pass filter 36, adder 15°17,
A high frequency noise reduction circuit constituted by a limiter 16 reduces high frequency components and extracts the signal. On the other hand, when a dropout occurs, the switch 7 is connected to the terminal 111, the output of the equalizer 37 is 111, and the output of the equalizer 37 is connected to the terminal 35. low pass filter 3G
The signal is replaced with the previous signal and taken out.

On the other hand, the output of the one-day delay circuit 35 is further delayed by 1H in a 1H delay circuit 38, the luminance signal component is removed by three bandpass filters, and the output is supplied to an adder 40 in reverse phase. Adder 3
The output of No. 4 is supplied to an adder 40 after the luminance signal component is removed by a bandpass filter '11 having the same delay amount as the bandpass filter 39.

11=1 delay circuit 35.38, 3 bandpass filters.

41. A 2H delay comb filter is configured in the adder 40, and cross 1 hake interference is removed.

This J: Uni invention circuit is in the Fli degree system (J
11-1 delay circuit used for drop error 1~compensation circuit, high frequency noise reduction circuit, and +#2 color sending signal system.
Since the configuration uses the 11" delay circuit used in the J-shaped filter, two 1l-Iff lines are required, which is 1" delay line compared to the conventional device. can be reduced by one.

FIG. 3 shows a block system diagram of the second embodiment of the circuit of the present invention, and the same components as in FIGS. 1 and 2 are numbered the same.
1 and its explanation will be omitted. In the same figure, /12 is (11''
-Δα) delay circuit, the output of which is a value obtained by reducing the storage amount Δα of the low-pass filter 36 from 1H in advance. As a result, the output of the low-pass filter 36 and the output of the reduction filter 11 are made to have the same timing.1. The equalizer 37 (FIG. 2) for the delay 1-U)Δ(χ correction which was necessary in the first example h1 is deleted 19.

/13 is a (11-1+Δα-Δβ) delay circuit, and its output horn is returned to the original timing by adding the delay iiiΔα that has been subtracted in advance by the (11-1-Δα) delay circuit 42, and This value is a value obtained by reducing the delay Δβ of the subsequent bandpass filter 4/I in advance. This allows the bandpass filter/
'The output of I4 is exactly 2l-(ff).
(FIG. 2) 17, the output of the bandpass filter 19 can be supplied as is to the adder /'IO.

The other configurations and operations are the same as those of the first embodiment, so their explanations will be omitted.

4r, 1['' delay circuit 35.38 and < 11-1-
The delay circuit 42, (11''-1-△α-80) delay circuit/13 needs to have a frequency band through which both the luminance signal and the carrier color (F+day) signal can pass.

Further, each of the delay circuits mentioned in a3 of the present invention may be a delay circuit using COD or the like, or a digital semiconductor method, etc. The band of the CCDJ extension circuit is 51 to 41 in the case of PAL system.
-1 z j: Although it is necessary, it currently exists, and there is no problem with 11j. In addition, using a decile semiconductor memory, there is one △D2 technique in the previous stage of the lζζ meeting, -1 in this 19th stage] △ change 1
g! In addition to requiring a memory address control for writing and reading memory, this can be easily done using a well-known technique.

What if a CCDW extension circuit is used? In the f81 embodiment, even if the drop error 1 is longer than 11'', it is only compensated for a period of 11'', and after that it becomes noise.

However, when a semiconductor memory is used, inputting the write-out bright period report into the address control results in a long drop error (11-1 or later by using the memory information multiple times). 1 q.

If a digital semiconductor memory is used as a delay circuit in this way, the recording signal or reproduction signal can be processed at a digital signal processing scale (1
When applied to a 4-component digital magnetic recording and reproducing device, the entire circuit can be easily reduced to 1 to 1 Sl, and the chip area can be saved to 1 q.
Ru.

In addition, each of the above embodiments is a one-type PΔl type, but N
The same applies to the TSC method19; in this case, four delay circuits are used in the latter stage.

Effect ten; As shown in d''r, the video signal processing circuit 1, 1 according to the present invention is provided with a means for adding the reproduced tl+degree signal and the reproduced carrier color signal, and a comb filter is installed. is composed of a delay circuit that delays the output of this means by 11-1 or 2 days, and a filter that removes the luminance signal component from the output of this delay circuit, and the dropout compensation tEt circuit is configured by the delay circuit and this delay circuit. It consists of a filter that removes the carrier color signal component from the output of the circuit, and a switch that switches between the output of the carrier color signal component removal filter and the reproduced luminance signal, so that the luminance signal system and the carrier color signal system can be separated separately. Compared to the conventional circuit using the Serinobu line, the total delay mother has been reduced to 11-
It has the characteristics that it takes less than 1 minute and the circuit can be configured more easily than conventional circuits.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an example of a conventional circuit, and FIGS. 2 and 3 are block diagrams of first and second embodiments of the circuit of the present invention, respectively. 4...High-pass filter, 5.36...Low-pass filter,
6...Drotubular 1~Detector, 7...Switch,
23°3/1. ．． 40... Adder, 33... Output terminal, 35°38... 1 day delay circuit, 36... Low pass filter, 37... Equalizer, 39. =1.1.4/
l...Band filter, 42...(11''-Δα) delay circuit, /I3...(1)-1+Δα-Δβ) delay circuit. Continued from page 1 0 Inventor Hidetoshi Ozaki Yokohama City Kanagawa Company

Claims (4)

[Claims] (1) The reproduced luminance signal and the reproduced carrier color signal are combined in a reproduced video signal processing circuit which extracts the reproduced luminance signal through a dropout compensation circuit and extracts the reproduced carrier color value silica through a comb filter. 11-1 A means for applying a comb filter is provided, and the output of the means is 11-1.
Alternatively, it is composed of a delay circuit that extends 2+-Iff and a filter that removes the luminance signal component from the output of the delay circuit, and is supplemented to the dropper 1 (transfers the circuit from the delay circuit and the output of the delay circuit). A reproduction I!II! image signal processing circuit comprising a filter for removing a color signal component, a switch for switching between the output of the carrier color signal component removal filter and a recording and reproduction luminance Shintan, etc. . (2) Claims characterized in that the delay circuit uses two 1-1 delay circuits connected in series, and the filter for removing the luminance signal component is connected to the cascade connection point. The reproduced video signal processing circuit according to item 1. (3) The reproduced video signal processing circuit according to claim 1, wherein the delay circuit is a COD delay line. (4) The reproduced video signal processing circuit according to claim 1, wherein the delay circuit is a digital semiconductor memory.