JPS62258579A - Frequency detection circuit - Google Patents

Abstract

PURPOSE:To allow a logic circuit to detect the input signal frequency by adopting a synchronizing logic circuit constitution using a D-FF. CONSTITUTION:D-FF 11, 14 and 17 are used to constitute a synchronizing sequence logic circuit satisfying equation. When the input signal frequency is 1/2 time of the horizontal scanning frequency fH, the detection signal of the 1st logic level is outputted. When the input signal frequency is fH/3 and fH, a pulse using the level of 1/3 and 1/2 time of the difference between the 1st logic level and the 2nd logic level as a mean value is outputted as a detection signal. Further, when the input signal frequency is fH/4, a pulse using the level of 1/2 or 3/4 time of the difference as a mean value is outputted as the detection signal.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a frequency detection circuit, and particularly to a circuit that detects a frequency 1/2 of the horizontal scanning frequency rH generated in the process of SECAM color video signal discrimination. ! LJru.

As is well known in the art, color television systems are not standardized worldwide, and each country or region adopts a predetermined color television system. However, depending on the area, it is possible to receive television broadcast signals of different color television systems from neighboring 11 stations, so two different color television systems (especially PAL and SECAM) can be received.
There are some areas where it is difficult to receive television broadcast signals of the same system.

For this reason, for example, V
When recording a TV broadcast signal using TR, check whether the TV broadcast signal you are trying to record is in PAL format or S E CA M.
A color television system discrimination circuit is required in order to automatically determine the color television system and switch the tuner, video signal processing circuit, etc. to operate optimally according to the color television system.

Conventionally, in this type of discrimination circuit, the color subcarrier frequency and color burst signal frequency of the PAL carrier color signal are 4.433619 MH2 (hereinafter, 4.43 MH2
), whereas in the SECAM system, the chroma non-modulated color subcarrier frequency is 4.40625 MHz (
(hereinafter referred to as 4.41 MH7) and 4.25 MH2,
Taking advantage of the fact that they are repeatedly transmitted alternately to 11-1, PAL and S
There was something that distinguished it from the ECAM method.

In FIG. 5, a color video signal inputted to an input terminal 1 is supplied to a burst gate circuit 2, where it is supplied from an input terminal 3, and is generated by known means.
The color burst signal or chroma non-modulated color Dj carrier wave is extracted by the burst gate pulse having a period of 11 (horizontal scanning period; the same applies hereinafter). As shown in Fig. 6, this extracted signal has frequency characteristics selected to have 4.16 MH2 as the center frequency of the pass band, to pass 4.25 MH7, but not to pass 4.41 MH2 or 4.43 MHz. It is supplied to a bandpass filter 4. Therefore, if the input color video signal is PAL format,
The output of the bandpass filter 4 is at an extremely low level;
In the case of the SECAM system, the output signal of the bandpass filter 4 is as shown in FIG. 7(A), with the unmodulated color subcarrier of 4.25 MH2 at a high level and the unmodulated color i! of 4.41 MH2. 1
The 112 transmitted waves are at a small level and have a waveform arranged in alternating H every 114 waves.

After the output signal of the bandpass filter 4 is subjected to envelope detection by the envelope detection circuit 5, it is converted to (1/2)・f'H.
1 of the horizontal scanning frequency fH.
A frequency component (approximately 7.8kl-1z) that is z2 times higher is detected. The output detection signal waveform of the envelope detection circuit 5 is as shown in FIG.
), and the envelope detection output signal of the unmodulated color subcarrier of 4.25MH2 is obtained with a period of 2H (that is, repetition frequency f'H/2), so this is the (1/2) fH detection circuit 6. Detected by On the other hand, when the input color video signal is a PAL color video signal, the output detection signal of the envelope detection circuit 5 is at an extremely low level and there is no repetition frequency component of (1/2)·fH. (1/2)·f The H detection circuit 6 does not detect it.

Therefore, from the (1/2)·f,1 detection circuit 6, the detection output (
For example, a substantially sinusoidal wave with a frequency f H/2) is obtained, and this detection output signal is integrated by the comparator circuit 7 and compared in level with a predetermined reference voltage, and then output to the output terminal 8. In this way, when the input color evening signal is of the SECAM system, a high level signal is outputted to the output terminal 8 as the SECAM system discrimination signal, and on the other hand, the P
In the case of the AL system, for example, a low level signal is taken out as a PAL system determination signal.

Problems to be Solved by the Invention By the way, (1/2) fH in the above conventional discrimination circuit
The detection circuit 6 was configured to amplify only the frequency component of (1/2)·fH using a tuned amplifier using an LC resonant circuit. Therefore, it is necessary to adjust the coil in order to adjust the resonance frequency of the LC resonance circuit to (1/2)·fH-+, and there are other problems such as poor temperature characteristics.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a frequency detection circuit that solves the above problems by having a synchronous sequential logic circuit configuration using D flip-flops.

Means for Solving the Problems The frequency detection circuit of the present invention has the following equation: Yn+1= (where X is the current input signal, xo-1 is the input signal one horizontal scanning period ago, Y is the current output signal, Yo -1
is a synchronous sequential logic circuit using flip-flops that satisfies the logical formula expressed as (output signal one horizontal scanning period ago), and the repetition frequency of the input signal is 1/2 times the horizontal scanning frequency fH. .

It is configured to output pulses of a constant logic level or a predetermined average value at each of 1/3 times, 1 times, and 1/4 times.

Operation The synchronous sequential logic circuit configured as described above outputs a detection signal of the first logic level when the repetition frequency of the input signal is 1/2ffi of the horizontal scanning frequency fH, and when the repetition frequency of the input signal is f' When H/3°fH, pulses whose average values are 1/3 and 172 times the difference between the first logic level and the second logic level are output as detection signals, and the input signal is repeated. When the frequency is f1/4, a pulse having an average level of 1/2 or 3/4 times the above difference is output as a detection signal.

Embodiment FIG. 1 shows a circuit diagram of an embodiment of the frequency detection circuit according to the present invention. The input terminal 10 is connected to a data input terminal DA of a D flip-flop 11 and one input terminal of an exclusive OR circuit (hereinafter referred to as an XOR circuit) 12, respectively. The other input terminal of the XOR circuit 12 is connected to the QA output terminal of the D flip-flop 11, and the output terminal of 17 data input terminal Dc. In addition, the input terminal 18 is
At the input terminal where the clock pulse of 1111H comes in, D
Each clock input b of flip-flops 11, 14 and 17
'15 children are connected to each other.

Further, the Qc output terminal of the D flip-flop 17 is connected to the data input terminal DB of the D flip 70 block 14 and one input terminal of each of the XOR circuit 13 and the two-way OR circuit 15, respectively. The other input terminal of the OR circuit 15 is connected to the Qe output terminal of the D flip-flop 14, and its output terminal is connected to the other input terminal of the NAND circuit 16. The Qc output terminal of the D flip-flop 17 is connected to the output terminal 19, from which the frequency detection circuit is taken out.

The logical formula of this circuit is the input signal n of the input terminal 10.
When n-1 is X, the input signal before IH is X, the output signal of output terminal 19 is Yn, and the output signal before IH is Y, then
It is shown by the following formula.

Yo"1- However, in equation (1), the value of each number 13 is the value at the time of the rise of the clock pulse, and at that time, it takes a logical value of "1" when it is high level and "0" when it is low level.

Next, the operation of the circuit having the above configuration will be explained.

An envelope detection signal from the envelope detection circuit 5 shown in FIG. 5 is input to the input terminal 10.

However, in this embodiment, the sixth band filter 4 is
As shown in the figure, it does not have a frequency characteristic, but has a passband center frequency at 4.5MHz7, 4.43MHz and 4.41MHz.
A bandpass filter is used that has a frequency characteristic that passes MH2 and greatly attenuates 4.25M1-(Z (for example, 20.B). Therefore, when a SECAM color video signal is received, , 4.25MH2 and 4.4
Of the two unmodulated carriers of 1MH7, 4.41
A P wave of MHz is passed through, and a pulse with a two-day cycle (pulse with a repetition frequency fH/2) of 1° as shown in FIG. 2 (A>) obtained by envelope detection of the P wave enters the input terminal 10. , when a PAL color video signal is input, 4.4
3 MH2 color burst signal is envelope-detected and has a daily cycle pulse <I as shown in Fig. 3 (A).
l! A pulse with a repetition frequency f ) l enters the input terminal 10 .

On the other hand, the input terminal 18 receives 1] 1 cycle pulse (as shown in FIG. 2(B) and FIG. 3(B)).
D flip-flops 11.1/- and 17 are applied to the -1 input terminals. The D flip-flop 11 combines the level of the input envelope detection signal F'iX with the rising edge of the clock pulse.
1 is output from its QA output terminal.

Therefore, when an envelope detection signal with a 2H period as shown in FIG. 2(A) enters the input terminal 10, a 2-day periodic square wave as shown in FIG. 2(C) is extracted as the signal X0-1. Moreover, when the envelope detection signal of 1H period shown in FIG. 3(A) is received, the signal of high level (first logic level) as shown in FIG. 3(C) is the signal X0-1.
is extracted as.

The XOR circuit 12 supplies a signal (xn-1.multidot.Xn) obtained by exclusive ORing the above signal x0-1 and the input signal X0 to the XOR circuit 13 together with the output horn signal Yn. On the other hand, D
The flip-flop 14 receives a signal obtained by sampling the output signal Yn supplied to its data input terminal D[l at the rising edge of the clock pulse, outputs it as Yn-1, and supplies it to the OR circuit 15 together with the output signal Y. do. XO
Both the output signals of the R circuit 13 and the OR circuit 15 are respectively supplied to the NAND circuit 16, and the NAND circuit 16 is NANDed to generate the signal Y0.
It is applied to the data input terminal Dc of the ID flip-flop 17, which is set to +1. The D flip 70 knob 17 outputs the signal g obtained by sampling the input signal Y0+1 of the data input terminal DC at the rising edge of the clock pulse at the output terminal 7-19.
etc. as a detection signal Y.

As a result, the input envelope detection signal
A>, when the signal has a 2H period, the D flip 70
QB output signal z of knob 14, Y n -1 is shown in the same figure (D>
The output signal Y becomes high level as shown in (E) of the figure, and the output signal Y also becomes high level as shown in (E) of the same figure. On the other hand, when the input envelope detection signal X is a signal with 111 periods as shown in FIG. The result is as shown in Figure (E).

Next, the above circuit operation will be explained in more detail with reference to the state diagram shown in FIG. In Figure 4, there are three D's for introverts.
The output level states of the respective Q output terminals QA, QB, and Qc of the flip-flops 11, 14, and 17 are shown, and the human input signal X/output signal Y0+1 is shown on the transition branch.

By inputting the S E CAM color video signal, the second
When an envelope detection signal with a repetition frequency fH/2 shown in the figure (A>) enters the input terminal 10, the input sequence (X) is 101010...・Changes to state 113
f (QA Q8 QC) will alternate between (111) and (011). At that time, the output series (
Y) becomes...111111... (Note that the 8 values of the input series and output series indicate the values at the rising edge of the clock pulse in Honkawa's Wl theory).

On the other hand, when a PAL color video signal is input, as shown in Fig. 3 (
When the envelope detection signal with the repetition frequency fH shown in Δ) comes in as the input signal RX, the input sequence becomes...111111... and the shape W (Q to QB
QC) changes alternately between (101) and (110), so the output series becomes...101010...

In this way, the output sequences for several periodic signal input sequences are summarized in the following table.

As can be seen from the table above and Fig. 1), but when an envelope detection signal with a repetition frequency fH (period 11) is received (when determining the PAL system), the above table and Figure 3 As you can see, the average output is 1 shift.
A symmetrical square wave with a period of 2H and /2 (a level midway between the difference between the high level and the low level) is obtained.

Note that if a bandpass filter with the frequency characteristics shown in FIG. 6 is used as the bandpass filter 4 shown in FIG.
When the L-format color video signal is input, the envelope detection signal remains at a low level as described above, but in this case as well, as can be seen from the table above, the output series becomes a symmetrical square wave with a period of 2H, and the average value is It becomes 1/2. Therefore, even if a bandpass filter 4 with the frequency characteristics shown in Figure 6 is used, and a bandpass filter with a passing center frequency of 4.5MHz is used, it is possible to discriminate between the PAL system and the SECAM system. I understand.

Also, as seen from the table above, the repetition frequency fH
/3 (period 31-1), the output signal is a pulse whose average level is 1/3 times the difference between the low level (second logic level "O") and the high level. Therefore, it is possible to sufficiently suppress the f l-1/3 signal component that may be manually applied to the input terminal 10 when a SECAM color video signal is input. Furthermore, as can be seen from the table above, the repetition frequency r H/4 (period JIIJ 4
For the input signal H), the output signal becomes b pulses having an average value of 3/4 or 1/2 of the level of the difference.

By passing this detection signal through a low-pass filter, extracting the DC component (output average Iil'r in the above table) and comparing the level with the standard voltage, it is possible to determine whether the system is a SECAM system or a PAL system.

It should be noted that the present invention is not limited to the above-mentioned embodiments, but includes all sequential logic circuits that satisfy the above formula (1).

Effects of the Invention As described above, according to the present invention, the repetition frequency (period) of the input signal can be detected using a configuration consisting of a Liebe logic circuit, so it can be made without adjustment and is stable against temperature changes. for reliable frequency detection, especially for SECA
(
1/2)・fH detection circuit.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing one embodiment of the circuit of the present invention, FIGS. 2 and 3 are signal waveform diagrams for explaining the operation of the circuit illustrated in FIG. 1, respectively, and FIG. 4 is a state diagram of the circuit illustrated in FIG. 1. , FIG. 5 is a block system diagram showing an example of a discrimination circuit of a conventional color television system, FIG. 6 is a frequency characteristic diagram of an example of a bandpass filter in the block system shown in FIG. 5, and FIG. It is a signal waveform diagram for explaining the operation of the illustrated block system. 6... (1/2) rH detection circuit, 10... Input terminal, 11.14.17... D flip 70 tube, 12
゜13... Exclusive logic sum circuit (XOR circuit), 16.
...NAND circuit, 18...clock pulse input terminal, 19...output terminal. Patent applicant: Victor Co., Ltd. Figure 1 Figure 2 (D) 1 (E) 1 → Kasuquestion

Claims (1)

[Claims] Y^n^+^1= @((X^n^-^1■X^n)■Y^n)・(Y^n
^-^1+Y^n) @(X^n is the current input signal, X^n^-^1 is the input signal one horizontal scanning period ago, Y
^n is the current output signal, Y^n^-^1 is the output signal from one horizontal scanning period ago) It is a synchronous sequential logic circuit using flip-flops that satisfies the logical formula expressed as The repetition frequency is 1/of the horizontal scanning frequency f_H.
When the frequency is twice, a detection signal of the first logic level is output, and when the repetition frequency of the input signal is f_H/3, and f_H, the detection signal is 1/3 of the difference between the first logic level and the second logic level.
Pulses with average values of twice and 1/2 times the level are output as detection signals, and the repetition frequency of the input signal is f_H.
1. A frequency detection circuit characterized in that the frequency detection circuit is configured to output, as a detection signal, a pulse whose average value is 1/2 or 3/4 times the level of the above difference when the difference is /4.