JPS5853511B2 - Method for manufacturing diodes incorporated into integrated circuits - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing diodes that are incorporated into integrated circuits.

FIG. 1 is a sectional view illustrating a conventional method.

In Figure 1, 1 is a P-type semiconductor substrate, 2 is an N-type epitaxial layer, 3 is a P+-type isolation region created by the upper and lower separation method, and 4 is an N+-type buried layer, all of which are based on semiconductor integrated circuit technology. This is well known.

Conventionally, when forming a Zener diode, a P region 7 with a higher concentration than the base region 6 is diffused into one island 5, and then base diffusion and emitter diffusion are performed on the other island 8 to form a transistor. During emitter diffusion, an N region 9 is diffused into a P region 7 to obtain a diode having desired Zener characteristics.

However, in the tilled soil method, in the emitter photoresist process that first determines the emitter diffusion region, mask alignment is performed based on the base region, so mask misalignment always occurs in P region 7 and N region 9, and furthermore, mask misalignment occurs in P region 7 and N region 9. Since the photoresist process for forming the electrode hole 10 is performed with reference to the base and emitter regions, mask displacement occurs, and due to these two mask displacements, there is a risk that the electrode hole 10 to the P region 7 may protrude from the P region 7. .

Second, the thickness of the oxide film 11 on the P region 7 increases due to the base and emitter diffusion of the transistor described above, and as a result, the base 6 of the transistor, which forms the electrode hole, the emitter 12, and the collector contact formed by the emitter diffusion. It is thicker than the oxide film on region 13, and electrode hole 10 tends to protrude from P region 7 due to side etching.

The present invention has been made in view of the drawbacks E, and provides a method for manufacturing diodes incorporated in integrated circuits that completely eliminates the conventional drawbacks. Examples will be described in detail.

In the present invention, as shown in FIG.
A type epitaxial layer 22 is provided, and a plurality of islands 24 are formed by separating the epitaxial layer 22 by an upper and lower separation region 23, and at least an N+ type buried layer 25 is provided in the island 24 where a transistor is formed. Well-known semiconductor integrated circuit technology is applied.

First, the desired islands 24 are diffused with diode P regions 26 .

The impurity coal dust in the P region 26 is 5×1O19CIrL″″3
The degree and base region are more concentrated and are formed before the base diffusion.

Subsequently, as shown in FIG. 3, another island 24 is subjected to base diffusion to form a base region 27 of a transistor.

A feature of the present invention is that the base is diffused in such a manner that it overlaps with the P region 26 during the base diffusion.

If this overlapping base diffusion is made to be approximately the same size as the P region 26 and completely overlapped in the base photoresist process,
Electrode holes 2 to the N region 28 and P region 26 in the subsequent process
Since all of the formations of 9 are based on the base diffusion, they are necessarily located within the P region 26.

In addition, the impurity concentration of the base diffusion is 5×1018CrIL-
Since the concentration is as low as about 3, the concentration change in the P region 26 is small and does not affect the Zener voltage much.

FIG. 4 shows a transistor emitter diffusion step, in which an emitter region 30 is formed within the base region 27 described above.

This emitter diffusion forms an N region 28 within the P region 26, completing a diode having Zener characteristics.

Further, in the transistor, a collector contact region 32 is formed in the collector region 31 .

Since the mask alignment of the emitter photoresist performed in this process is performed with the base region 27 as a reference, the N region 28 is reliably covered with the P region 2 overlapping the base diffusion as described above.
It falls within 6.

After that, as shown in FIG.
is formed.

The electrode holes are formed using photoresist technology, and since the photoresist mask alignment is based on both the base diffusion and emitter diffusion, the electrode holes 29 to the P region 26 are reliably connected to the P region.
Located within area 26.

Electrode holes to the N region 28, emitter region 30, base region 27 and collector contact region 32 are also formed by etching.

According to the method of the present invention, by performing base diffusion almost overlapping the P region 26, all mask alignment in the subsequent process can be performed based on the base diffusion standard, completely eliminating mask misalignment. .

However, in such a method, the surface concentration of the P region 26 decreases slightly due to the oxidation heat treatment due to base diffusion, which causes variations in the Zener breakdown voltage.

Further, when a high Zener withstand voltage is required, the surface concentration of the P region 26 is designed to be low, for example, about 2×10 19 cfrL −3 , so that the concentration change due to base diffusion cannot be ignored, making it impossible to apply the tilling method.

FIG. 5 shows an embodiment that improves this point.

In this example, as is clear from FIG. 5, the base diffusion portion 34 overlapping with the P region 26 is limited to only the portion where the electrode hole 29 to the P region 26 is formed.

Therefore, in mask alignment during base diffusion, it is preferable to overlap the overlapping portion 34 to the P region 26 with the part of the side where the electrode hole 29 to the P region 26 is to be formed, as shown in FIG.

In FIG. 6, the dotted line indicates the N region.

This method also allows the P region 26 to be used as the same reference as the base diffusion, thereby eliminating mask misalignment in subsequent steps.

Further, in the two embodiments described above, the electrode hole 2 to the P region 26
9 has a thickness equal to that of the oxide film 33 in the base region 27 of the transistor because the base diffusion is superimposed, and protrusion from the P region 26 due to side etching is also prevented.

As described in detail above, the present invention is advantageous in that by superimposing the base diffusion on the P region, mask alignment based on the base diffusion can be performed and mask shift can be completely eliminated.

[Brief explanation of the drawing]

FIG. 1 is a sectional view illustrating a conventional example, FIGS. 2 to 5 are sectional views illustrating the present invention, and FIG. 6 is a partial top view of FIG. 5. Description of main drawings, 21 is a semiconductor substrate, 22 is an epitaxial layer, 23 is an isolation region, 24 is an island, 25 is a buried layer, 26 is a P region, 27 is a base region, 28 is an N region, 2
9 is an electrode hole, and 30 is an emitter region.

Claims (1)

[Claims] 1. After diffusing and forming a high concentration P region before base diffusion,
Base diffusion is performed by overlapping at least a portion of the P region, the N region is diffused into the P region by emitter diffusion, and the oxide film on the base-diffused portion of the P region and the N region are respectively A method of manufacturing a diode incorporated into an integrated circuit, comprising forming electrode holes. 2. A method of manufacturing a diode incorporated in an integrated circuit according to claim 1, characterized in that the base diffusion is substantially overlapped with the P region.