JPS5853439B2 - Memory Seigiyohoushiki - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory control system, particularly a data processing system configured to perform retry processing on the memory in response to an error detected in data read from the memory. In the system, data is stored in the memory with an error correction code added, an error correction circuit is added, and the existing NoriTry process is replaced.
The present invention relates to a memory control system in which data corrected by the error correction circuit is supplied to a target circuit as if it were data as a result of retry processing.

In recent relatively small data processing systems, when there is an error in data read from memory, a retry process is generally performed to read the memory again.

However, it has become desirable for this type of data processing system to also have an error correction processing function.
When this function is provided, errors can be corrected, so there is no need to read them again in retry processing.

Therefore, it is necessary to correct the error instead of reading it again.

The present invention aims to solve the above points,
It is an object of the present invention to utilize the existing retry processing function as it is and to perform error correction processing by replacing the retry processing with a simple configuration.

Therefore, the memory control method of the present invention includes a memory, an error detection function that detects the presence or absence of an error in data read from the memory, and a memory that instructs re-reading or sends a try signal to the memory in response to the occurrence of an error. A data processing system equipped with a re-reading mechanism for supplying data to the memory, which stores data with an error correction code attached to the data stored in the memory, and receives the read data attached with the error correction code. an error detection circuit configured to detect the presence of an error and provide an error detection signal to the rereading mechanism to prompt an IJ) lie;
An error correction circuit receives the read data and performs error correction processing, and prohibits access to the memory based on the retry signal generated by the rereading mechanism in response to an error detection signal from the error detection circuit. IJ that transfers the above error correction circuit output to the target circuit without re-reading the data by trying.
It is characterized by having an I-Ly processing switching circuit.

This will be explained below with reference to the drawings.

FIG. 1 shows the configuration of an embodiment of the memory control method of the present invention, and
The figure shows a time chart explaining the process.

In the figure, 1 is a memory, 2 is an error detection circuit, 3 is an error correction circuit, 4 and 5 are AND circuits, 6 is an OR circuit, 5TA
RT is a memory access start signal, RTY is a retry signal, ERROR is an error occurrence signal, a, by...
・h represents the signal at each point shown in the figure.

As mentioned above, relatively small-sized data processing systems generally have a function of re-reading the memory or performing a trial process when there is an error in data read from the memory.

A program for retry processing is also prepared accordingly.

In this type of data processing system, it may be considered to provide a data correction function according to the user's wishes.

In this case, redesigning a data processing system with data correction functionality becomes expensive.

Therefore, it is desirable to be able to easily respond to the user's wishes, whether the data processing system has a data correction function or the data processing system has a retry processing function.

Therefore, in the case of the present invention, an error correction circuit is added to an existing small-sized data processing system that issues a retry signal in response to the occurrence of an error when there is an error in read data, and a retry process that switches the retry process. A processing switching circuit is provided to provide an error correction function.

In order to provide the error correction function, an error correction code is added to the data stored in the memory 1.

Memory access start signal 5T for memory 1
Each time ART becomes logic "1", signal C becomes logic "1" and memory 1 is accessed as shown in FIG.

Then, data is read out from the memory 1 with a certain time delay as shown in FIG. 2 (signal f).

The data is transferred to the target circuit via the OR circuit 6.

At this time, the read data is simultaneously guided to the error detection circuit 2 and the error correction circuit 3.

If an error exists in the data, the error detection circuit 2 issues an error occurrence signal ERROR, and the error occurrence signal is notified to the error correction circuit 3, the program, and the target circuit.

It may be considered that the target circuit discards the previously received data, assuming that the data contains an error.

When the error occurrence signal ERROR is notified to the program, the program issues retry signals R and TY according to existing functions.

During this time, the error correction circuit 3 performs automatic error correction processing on the previously read data in which an error exists, using an error correction code.

When the retry signal RTY becomes logic "1", the AND circuit 4 is disabled and the next memory access
Even if the start signal 5TART becomes logic "1", the memory 1 will not be accessed.

That is, access to memory 1 according to the retry process is prohibited.

On the other hand, the retry signal RTY becomes logic "1" and the memory access start signal 5TART becomes logic "1".
Then, the AND circuit 5 is turned on and the error correction circuit 3
is notified in the form of signal d.

Along with this, the error correction circuit 3 transfers the data automatically corrected during this period to the target circuit via the OR circuit 6 as a signal g.

That is, in the program and the target circuit, it is recognized that the existing Nori-try processing is being executed, but in the memory control, the IJ l-rai processing is replaced,
The data corrected by the error by the error correction circuit 3 is transferred to the target circuit.

It goes without saying that in the configuration shown in FIG. 1, a wired OR circuit can be used in place of the OR circuit 6 in order to simplify the configuration.

The present invention makes it possible to provide an error correction function with a simple configuration as described above, and also includes the following major advantages.

That is, in data processing systems that conventionally have an error correction function, data read from memory is generally
Anticipating that an error may exist, the data is configured to wait for processing by the error detection circuit 2 and error correction circuit 3 before being transferred to the target circuit.

For this reason, in a data processing system having an error correction function, the access time is short because the system waits until the above processing is executed.

However, in the case of the present invention, the data read from the memory 1 is transferred as is to the target circuit for use, and the target circuit receives correct data only when an error is detected.

Therefore, access time does not become long.

As explained above, according to the present invention, by adding a simple configuration, it is possible to provide an error correction function in response to the user's wishes, and by providing the error correction function, one access time can be reduced. will not increase.

[Brief explanation of the drawing]

FIG. 1 shows the configuration of an embodiment of the memory control method of the present invention, and
The figure shows a time chart explaining the process. In the figure, 1 is a memory, 2 is an error detection circuit, 3 is an error correction circuit, and 4 and 5 are retry processing switching circuits.

Claims (1)

[Claims] 1 A memory, an error detection function that detects the presence or absence of an error in data read from the memory, and a rereading mechanism that instructs rereading or supplies a try signal to the memory in response to the occurrence of an error. In a data processing system, the data processing system is configured to store data with an error correction code attached to the data stored in the memory, and to detect the presence of an error by receiving the read data attached with the error correction code. an error detection circuit that supplies an error detection signal that prompts the rereading mechanism to retry; an error correction circuit that receives the read data and performs error correction processing; and an error detection signal from the error detection circuit. Prohibiting access to the memory based on the retry signal generated by the rereading mechanism in response to the above, and transferring the output of the error correction circuit to the target circuit or switching the try processing without rereading the data due to the try. A memory control method characterized by the addition of a circuit.