JPS5853222A - Analog-to-digital converter - Google Patents

Abstract

PURPOSE:To eliminate the unstable operation of a comparator consisting of an N-MOS and to realize highly precise conversion, by setting the first comparing reference potential of a successive comparison type A/D converter at 3/4 reference voltage. CONSTITUTION:An anlog input 24 of a successive comparison type A/D converter turns on S1, S2 and S4 and is sample-held at a capacitor C1. Then S1, S3 and S4 are turned off with the S2 turned on, and the comparison with the reference potential 22 is carried out through a comparator 2 consisting of amplifiers Tr1 and Tr2 of an N-MOS. Then the output 23 is successively fed to a comparison controlling part to change the reference potential. The own bias of the Tr1 is set at 1.4V, and the comparing reference potential is set 3/4 reference voltage 5V with an input set at 5V. Thus the potential of a terminal C11 is set at 1.4-(5-3.75)V and positive. As a result, a forward current produced by a p-n junction does not flow to realize the use of an amplifier of high gain. In such way, a conversion is possible with high precision.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an analog-to-digital converter, and more particularly to a sequential comparison type analog-to-digital converter made using MO8 technology.

MOS sequential comparison type analog-to-digital converter (hereinafter referred to as A
DO) will be explained with reference to FIGS. 1 to 3.

FIG. 1 is a basic block diagram of a sequential comparison type ADC, and FIG. 2 is an example of a reference potential generation section that generates a reference potential.
FIG. 3 shows one embodiment of a sample-and-hold device and a voltage comparator. These figures 1 to 3 show the conventional ADC and the ADC of the present invention.
It can be applied to both DC and DC.

To explain in detail with reference to Fig. 1, analog human power 21
and a reference potential 22 by the voltage comparator 2, and based on the comparison result 23, the sequential comparison control section 3 controls the reference potential generation section 1 via the control line 11. Generally, the sequential approximation algorithm is performed by the sequential comparison control section 3.

The conventional successive approximation algorithm first uses analog human power24
is sampled by a sample-and-hold device 4, and then the sampled input analog signal 21 is compared with a reference potential 22 from a reference potential generator by a voltage comparator 2. The first comparison is the sampled analog input signal 21 and the reference voltage ■
Compare with VR/2 which is half of R. Based on the comparison result, it is compared with a reference potential of 3/4 VR or 1/4 VR. If the analog human power 24 is larger than V n /2, compare it with 3/4 VR, and if it is smaller, compare it with 1/4 VR.
Compare with.

Similarly, the next comparison potential is determined based on the comparison result.

Such control is performed by the sequential comparison control section 3. That is, the sequential comparison control section 3 first sets the reference voltage Vll
The maximum bit output is set to binary 1 so that the reference potential 22 is output at the midpoint of . The reference potential 22 and analog input 21 are compared, and if the analog input is greater than the reference potential 22, the maximum bit output remains a binary 1. However, if the analog input is smaller than the reference potential 22, the maximum bit output changes from binary 1 to binary 0.

Next, the next highest digit bit output is set to binary 1, and the reference potential 22 and the analog input 2 corresponding to that binary number are set.
Compare with 1. In this way, the same operation is repeated from the largest bit to the smallest bit to convert it into a binary number equivalent to the analog input. For a more detailed explanation of this sequential comparison control, please refer to JP-A No. 52-28851.

The fact that this conventional sequential comparison algorithm is not suitable for a high-precision ADC will be explained using N-MOS as an example with reference to FIGS. 3 to 5.

FIG. 3 shows a preferred embodiment of a sample-and-hold device and a voltage comparator. First, during a sample period t1, switch S1. S3
and 84 are turned on to sample and hold the analog human power 24.

The terminal CIO of the capacitor C1 is set up to the potential of the analog human power 24, and the terminal C11 is set up to a self-bias potential due to a short circuit with the input by the switch S3. Similarly, switch S4 sets up Tr2 to the self-bias potential. Self-biasing eliminates the need for additional bias voltages and solves the problems of bias sensitivity and offset caused by supply voltage variations.

In addition, the capacitors C1 and C2 are connected to an amplifier Trl.

Tr2 is AC coupled.

FIG. 4 shows the input characteristics 51 of the enhancement load type transistor. An intersection 52 between the 45° straight line and the input/output characteristic 51 is a self-bias point, and the self-bias potential Vt is a potential slightly higher than the threshold potential of the enhancement type transistor.

通ONON-MO57'i sextefd+ 1.2~+
There is 1.5 Vte. Here, the explanation will be made assuming that Vt=-1-1.4V.

The sample and hold of the analog input ends, and the first comparison period t2 begins. First, switch S1+83+S4
is turned off, and then switch S2 is turned on to connect reference potential 22 to terminal C1o.

Since the capacitor C1 is AC coupled to the amplifier Tr1, the difference between the analog input potential and the reference potential is transmitted to the amplifier Tr1 by the capacitor C1.

This potential difference is the amplifier Tr1. The comparison result 23 is amplified by Trz and is sequentially input to the comparison control section 3.

The sequential comparison control section 3 generates the next reference potential 22 based on the comparison result 23 and performs the second comparison. (Period t3) Here, the accuracy of the ADC is determined by the comparator 2, that is, the amplifier T.
r1. Since it largely depends on the gain of Trz, it is necessary to design the gain to be as high as possible. FIG. 5 shows the potential of the terminal C1l. Reference voltage VR-+5v, analog input VIN: +5v self-biased voltage Vt=-+ 1.4v
,! : Explain. Normally, during the sample and hold period t1, the self-bias wake-up pressure Vt (~+1.4V)9, and during the first comparison period t2, the reference potential VB/2 = 5
V/2= + 2.5 v) is applied to the terminal CIO, and the i-coder Co11: (+1.4v-3,5v)-1
, becomes 1v. When the terminal C11 becomes a negative potential, the N-P junction becomes forward, a forward current flows, and self-bias'
The potential held at the awakening pressure fluctuates greatly, greatly impairing the quality of forgeries.

In order to eliminate this drawback, conventionally the analog input VIN was set to 0.
It is limited to about +3v, but the amplifier 'I'rl, 'I
By significantly increasing the self-bias voltage of 'r2,
．． The method used was to set it to 5V. Restricting the analog input greatly narrows the range of applications for Al)C. Amplifier Tr1. To significantly increase the self-bias voltage of Tr2, the gain of the amplifier must be significantly lowered. A low gain amplifier has the disadvantage that the accuracy of the ADC deteriorates.

The object of the present invention is to eliminate the above-mentioned drawbacks and to provide a highly accurate ADC without limiting the analog input range.

An analog-to-digital converter according to the present invention includes a sample-and-hold device receiving an analog input, a reference potential generator for generating a reference potential, and an output signal representing a comparison between the output of the sample-and-hold device and the reference potential. a successive comparison control section for controlling the reference potential section according to the output signals of the comparators; It is characterized in that it is carried out at a potential of .

According to the present invention, since the voltage at the terminal C1l of the capacitor C1 is first compared with 3/4 of the reference voltage, the potential at the terminal C1l of the capacitor C1 is Vt-('VIN-3/4V) even during the first comparison period t2. Even the worst value was +0.15 v')
There is no NP concubinage effect. Therefore, the gain of the amplifier can be increased and the analog input range can be widened, making it possible to provide a highly accurate analog-to-digital converter.

An embodiment of the present invention will be described with reference to FIGS. 1 and 6. The configuration of the analog-to-digital converter of the present invention is the same as that shown in FIG. 1 described above, but the present invention is controlled by a sequential comparison algorithm suitable for high-precision conversion. FIG. 6 shows an embodiment of the sequential comparison control section of the present invention.

In the implementation described here, the known technique shown in FIG. 2 is used as the reference potential generator, and the known technique shown in FIG. 3 is used as the sample/hold and comparator. The sequential comparison control section in FIG. 6 includes 5-bit shift registers 31a to 31e,
3-bit R-1 flip-flops 32a to 32C and 5
or gates 34a to 34c, 35a to 35b
It consists of ′. Or Gate 34a-34C
The outputs A and C□ are based on the standards shown in Figure 2, and are
controlling the switch. The output of the shift register 31a controls a sample-and-hold device and a comparator. The embodiment has the same parameters as the conventional example, that is, the reference voltage V
R=+5v, analog human power VIN=+5v, and self-bias potential Vt=+1.4v will be explained. First, when 1# is set in the shift register 31a, the outputs become "1" and the switches Sl, S3 . Turn on S4, analog human power 24 sampling and amplifier Tr! , Tr2 is set up to a self-bias potential. Furthermore, by the reset signal 33, J) R-S flip-flops 32a to 3
Also reset 2C. (Period 11) Next, when the contents of the shift register 31a are transferred to the shift register 31b, the output of the shift register 31a becomes PA0#, and the output of the shift register 31b becomes °1''.Then, the switch S1
．． S3 and S4 are turned on, and switch S2 is turned on to perform comparison with the reference potential. The output of the shift register 31b is 1
When # is reached, the control outputs A and B remain at "1" and the control output C remains at "10" due to the control outputs 34a and 34b. Therefore, the control outputs 9-A, B, and C remain at 2. It is applied to the terminal C1o of the base capacitor C1 in FIG. 2, and VIN--"-VD
is the width increase i%Tr1. Trs+ is amplified, and the comparison result 23 becomes the cent input of the 1t-S flip-flops 32a to 32C of the sequential comparison control section 3. During the period t2, the shift register 31b is "'1" (or game) 35a,
35b by L%-87 Lip 70 Tsug 32a and 32b
is selected. Also, VIN −−Ve = 5v−
'x4 5'=+1.25 The ratio V is 1''.

Therefore, 几-S flip-flops 32a and 32b are set.

In the next comparison period t3, the contents of the shift register 31b are transferred to the shift register 31c. However, LL-S
Unless the flip-flops 32a and 32b are set, (, to, B, C) = (1, 1, 0) and the period t2
Perform the same operation as .

During the ratio fi1 interval t4, the contents of the shift register 31c are transferred to the shift register 31d. However, since the R-S flip-flops 32a and 32b are set to 10-, the same operation as at t3 is performed. In the last comparison period t5, the contents of the shift register 31d are transferred to the shift register 31e, so (A, BC) =
(1, 1, 1), and the reference potential 22 of 100 VR is output and compared by the comparator.

In the period t5, the R-S flip-flop 32C is selected because of the shift register 31e's value "'1", and p is set according to the comparison result (vIr+-i-'V'R).

At the end of this period t5, ■ts flip-flop 32
The same contents of a to 32c are transferred to the conversion result registers (all shown in the figure), and the shift registers 31a to 31e are reset.

Between t1 and t5, the terminal C110 of the capacitor C1
The topography is shown in Figure 7. MbJJtx is self-biased to <Vt −+1.4V, which is the same as in the conventional example.

During period t2 to t4, Vt-(MIN-, VB) =+
0.15V! :;/UV't in ts between cDM (
vIN-ヱVe) = +0.775''), C1
Since the potential of 1 is above Ov throughout the entire period, 1'
Since no forward current flows due to Ni coupling, a high-gain amplifier can be used and zero-accuracy analog-to-digital conversion is possible.

The invention is highly effective when the precision of analog-to-digital conversion is 10 bits or more and the sensitivity of the comparator must be 1 to 2 mV or less. That is, the conventional method cannot lower the self-bias potential due to the NP junction effect. Therefore, the gain of the amplifier cannot be increased. However, according to the present invention, since there is no NP junction effect, the gain of the amplifier can be made sufficiently high.

In the detailed description of the present invention, VIN=+5v.

Ve=+5',"'t=+1.4Ve for ear cJ(,
The production of VIN=Ov is compared with analog human power using the following L criteria - K rank.

Period t2 (A+B+C) −(1r 1 v O)
Mutual VRJtJRIl t3(A, B, C) = (
1, 0, 0) Upper VR period it (AtE, C) =
(c+, t, o) Upper VR

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a sequential comparison type analog-to-digital exchange, which is common to the conventional system and the present invention. FIG. 2 is a circuit diagram of the reference potential generation section, and FIG. 3 is a circuit diagram of the sample/hold section and comparator. FIG. 4 is an input/output characteristic diagram of the MOS inverter. FIG. 5 shows the potential waveform of the terminal C1l of the capacitor C1 in the conventional method. FIG. 6 is a circuit diagram of an embodiment of the sequential comparison control section of the present invention. FIG. 7 shows the potential waveform of the terminal C11 of the capacitor C1 in the sequential comparison method of the present invention. 1...Reference potential generation section, 2...Comparator, 3...Sequential comparison control section, 4...Sample/hold section. 13- Chin 1 Figure 2 Figure 4 Figure 5 Figure 7

Claims (1)

[Claims] A sequential comparison type analog-to-digital converter includes a sample and hold device that receives an analog input, a reference potential generation section that generates a plurality of reference potentials, and a comparison between the output of the sample and hold device and the reference potential. a comparator that generates an output signal representing the reference voltage VB; and a sequential comparison control section that controls the reference potential generation section according to the output signal of the comparator, and the first comparison is performed at 3/4 of the reference voltage VB. An analog-to-digital converter, characterized in that the conversion is performed using a potential and an output of the sample-and-hold device.