JP2956119B2 - Parallel A / D converter - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel type A / D converter, and more particularly to an input / output characteristic of a parallel type A / D converter which is generated by a current flowing from a connection point of a comparison voltage generating resistor to a comparator. The present invention relates to a parallel A / D converter configured to reduce a nonlinearity error.

[Summary of the Invention]

The parallel A / D converter of the present invention includes a plurality of resistors connected in cascade with each other, an input signal and a voltage at each connection point of the plurality of resistors supplied as a reference voltage, and a plurality of differential resistors. A comparator including a transistor pair, a gate circuit to which an output of the comparator is supplied, and an encoder to which an output of the gate circuit is supplied, and one of the differential transistor pairs is turned on simultaneously when both transistors are turned on. A non-linearity error in input / output characteristics is reduced by providing a constant current source that supplies a current substantially equal to a current flowing into an input electrode of the transistor to a connection point of the plurality of resistors.

[Conventional technology]

2. Description of the Related Art Conventionally, a linearity compensation circuit of a parallel A / D converter has been known as described in, for example, JP-A-63-198419.

That is, in the block diagram of the conventional parallel A / D converter shown in FIG. 9, 1 is a comparison voltage generation circuit,
Connect 256 resistors R ₁ through R ₂₅₆ as an example between the power supply terminal 0V and -2 V, generating a different comparison voltages to the respective connection points. Reference numeral 2 denotes a comparator, 3 denotes a gate circuit, and 4 denotes an encoder, which outputs 8-bit digital signals D _{1 to} D ₈ to the output of the encoder 4. 5 is a linearity compensation circuit, respectively supply predetermined current 64i in the resistor R ₁ to the predetermined connection points of R ₂₅₆ Nd ₁ to Nd _3.

In the above configuration, the resistors R _{1 to} R ₁ of the comparison voltage generation circuit 1 are controlled by the current 64 i supplied from the linearity compensation circuit 5.
The linearity of the input / output characteristics of the converter, which is impaired by the current i flowing from each of the ₂₅₆ connection points to the comparator 2, can be compensated.

[Problems to be solved by the invention]

However, in the above-described conventional parallel A / D converter, when the input stage of the comparator 2 is constituted by an emitter follower, the resistor R ₁ of the comparison voltage generating circuit ₁
To the current flowing from the connection point of the R ₂₅₆ to the comparator 2 i
Is constant with respect to the change in the input voltage, so that the linearity compensation is performed favorably. However, when a low-voltage integrated circuit is used, the current i flowing through the comparator 2 changes according to the change in the input voltage when the input-stage emitter follower of the comparator 2 is omitted in order to expand the dynamic range. Was difficult to compensate for linearity.

Accordingly, an object of the present invention is to provide a parallel type A /
It is to provide a D converter.

[Means for solving the problem]

The parallel A / D converter of the present invention includes a plurality of resistors connected in cascade with each other, an input signal and a voltage at each connection point of the plurality of resistors supplied as a reference voltage, and a plurality of differential resistors. A comparator including a transistor pair, a gate circuit to which an output of the comparator is supplied, and an encoder to which an output of the gate circuit is supplied, and one of the differential transistor pairs is turned on simultaneously when both transistors are turned on. A constant current source for supplying a current substantially equal to the current flowing into the input electrode of the transistor to the connection point of the plurality of resistors is provided.

[Action]

According to the parallel A / D converter of the present invention, even when the emitter follower stage is not provided in the first stage of the comparator, when both transistors of the differential transistor pair are simultaneously turned on, the current flows into the input electrode of one transistor. A current substantially equal to the current is supplied from the constant current source to the connection point of the plurality of resistors to compensate for the current flowing from the connection point of each resistor to the comparator, thereby reducing the non-linear error of input / output characteristics and inputting. The error at the time of 1/2 input of the maximum level of the signal can be minimized.

〔Example〕

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the basic configuration of a parallel A / D converter according to the present invention. Reference numeral 6 denotes a terminal for supplying a voltage V _ref (for example, 0 V), and reference numeral 7 denotes a voltage V _rb (for example, a negative voltage). Is a terminal for supplying R _{1 to} R ₈ (for example, a case of 3 bits) are first to eighth resistors, which are cascaded between terminals 6 and 7. CCS ₁ to CCS ₇ is a constant current source of the first to seventh, supplies a predetermined current i / 2 to be described later to a connection point P ₁ to P ₇ of the first to eighth resistor R ₁ to R ₈ . 8 is a comparator, which is a first differential transistor pair
It has Q ₁ , Q _{2 to} seventh differential transistor pairs Q ₁₃ , Q ₁₄ (however, the second differential transistor pair Q ₃ , Q _{4 to} sixth differential pair)
Q ₁₁ and Q ₁₂ are not shown). The first differential transistor pair
The input electrode (base) of _one transistor Q ₁ of Q ₁ and Q ₂ is supplied with the reference voltage of the connection point P ₁ and the other transistor Q ₁
The input electrode Q ₂ 'input signal V _in at the input terminal 9 is supplied. Incidentally, B _u1 to B _U7 (B _u2 to B _u6 is not shown) is a buffer stage. If the first common current source CC ₁ of the current of the differential transistor pair Q _1, Q ₂ and i _0, the input signal V at the input terminal 9
_in the first differential transistor pair Q _1, Q ₂ are turned on when equal to the reference voltage at the connection point P _1, the current flowing into the input electrode of the transistor Q ₁ (basis) _{i 0/2 (1 + h} fe ) = I / 2
become. Then, the first to seventh constant current sources CCS _{1 to} CCS ₇
Current value flowing into the plurality of connection points P ₁ to P ₇ from is set to i / 2. 10 is a gate circuit which outputs are supplied from the comparator 8, a gate G ₁ to G ₇ (however, the gate G ₂ to the gate G ₆ are not shown). 11 is the gate circuit 10
Output is supplied, an encoder for generating a digital signal D ₁ through D ₃ of 3 bits. Note that CC ₇ is a common current source for the seventh differential transistor pair Q ₁₃ and Q ₁₄ .

The operation in the above configuration will be described with reference to the circuit diagrams of the main parts used for describing the present invention in FIGS. 2 to 8.

In FIG. 2, the current flowing from terminal 6 to terminal 7 is represented by I
And then, the input signal V _in supplied to the input terminal 9 is a connection point P ₁
It explained equal to the reference voltage V _a. V _a = V _in
At this time, the first differential transistor pair Q ₁ and Q ₂ are both turned on, and a current i / 2 flows through the input electrode of the transistor Q ₁ , so that the voltage V _{rb at the} terminal 7 is expressed by the following equation.

V _rb = −8RI− (21/2) iR (1) where R is a resistance value of the _{first to} eighth resistors R _{1 to} R ₈ .

 When RI is obtained from equation (1), equation (2) is obtained.

RI = If _{(- - V rb (21/2)} iR) / 8 ...... (2) (1) and (2) determining the voltage V _a of the connection point P ₁ from, the following expression is obtained.

Thus, the first differential pair input electrode of the transistor Q ₁ i / 2
The error voltage due to the flow of current is 21 iR / 16,
CCS ₁ to the constant current source can be greatly reduced than the error voltage 4iR when no CCS _2.

It will now be described the circuit diagram of a main part used for the case where the input signal V _in is equal to the reference voltage V _b at the connection point P ₂ in the description of the present invention of FIG. 3.

In FIG. 3, when V _in = V _b, the transistor to Q ₁ first transistor pair Q _1, Q ₂ are turned on, the transistor
Q ₂ turns off. In addition, since the transistors Q ₃ and Q ₄ of the second transistor pair Q ₃ and Q ₄ are both turned on, the transistors
The current of i flows through the input electrode of Q _{1 and} the transistor Q ₃
The current at the terminal 7 is expressed by the following equation since a current of i / 2 flows through the input electrode of

V _rb = −8RI− (16/2) iR (4) When RI is obtained from equation (4), equation (5) is obtained.

RI = If _{(- - V rb (16/2)} iR) / 8 ...... (5) (4) and Formula (5) obtains the voltage V _b at the connection point P ₂ from the equation, the following equation is obtained.

Accordingly, the first differential transistor pair Q _1, Q ₂ of the transistor Q ₁ and a second differential transistor pair Q _3, transistor Q ₄
Error voltage by the current flowing through the Q ₃ are the 3IR / 2.

It will now be described the circuit diagram of a main part used for the case where the input signal V _in is equal to the reference voltage V _c at the connection point P ₃ to the description of the present invention of FIG. 4.

In Figure 4, when V _in = V _c, the transistor to Q ₁ first transistor pair Q _1, Q ₂ are turned on, the transistor
Q ₂ turns off. The transistor Q ₃ of the second transistor pair Q _3, Q ₄ are turned on, the transistor Q ₄ is turned off and transistor Q _5, Q ₆ of the third transistor pair Q _5, Q ₆ are both turned on , transistor Q ₁ and transistor
Voltage V _rb terminal 7 since the input electrode of Q ₃ current i is i / 2 current flows through the input electrode of the transistor Q ₅ with flowing respectively is expressed by the following equation.

V _rb = −8RI− (13/2) iR (7) When RI is obtained from equation (7), equation (8) is obtained.

RI = If _{(- - V rb (13/2)} iR) / 8 ...... (8) (7) and (8) determining the voltage V _c at the connection point P ₁ from, the following expression is obtained.

Accordingly, the first differential transistor pair Q _1, Q ₂ of the transistor Q ₁ and a second differential transistor pair Q _3, transistor Q ₄
Error voltage caused by the current flowing through the transistor Q ₅ of Q ₃ and third differential transistor Q _5, Q ₆ is a 15iR / 16.

Similarly, the error voltage when V _in = V _d in FIG. 5 is zero, the error voltage when V _in = V _e in FIG. 6 is a -15iR / 16. Next, an error voltage at the time of Vin = _{Vf in} FIG. 7 is obtained.

Since the voltage V _rb is as follows: V _rb = −8RI− (16/2) iR (10) Therefore, when RI is obtained from the equation (10), RI = (− _Vrb− (16/2) iR ) / 8 .... (11), and the reference voltage V _f at the connection point P ₆ is _{V f = -6RI- (1/2) iR} × 15 = (6/8) V rb - (3/2) iR ... ... determined to be (12), so that the error voltage is -3iR / 2 is a deviation from the ideal voltage (6/8) V _rb when ignoring the base current of the transistor.

Next, determine the error voltage when V _in = V _g in Figure 8. Voltage V _rb, since a _{V rb = -8RI- (21/2) iR} ...... (13), when obtaining the RI from the (13) _{formula, RI = (- V rb -} (21/2) iR ) / 8 .... (14), and the reference voltage V _g at the connection point P ₇ is _{V g = -7RI- (1/2) iR} × 21 = (7/8) V rb - (21/16) iR ... ... determined to be (15), so that the error voltage is -21iR / 16 is a deviation from the ideal voltage (6/8) V _rb.

As is apparent from the description of FIG. 2 to FIG. 8 described above, the error voltage of the present invention is maximum at -3IR / 2 when the input signal _{V in = V b, V in} = V f, V in = V becomes minimum (0) when _d (1/2 input), but as compared with the case where in any case not provided a constant current source CCS ₁ to CCS ₂ can be significantly reduced error voltage.

Note that, in the above-described embodiment, an example of 3 bits has been described, but 8 bits, 12 bits or more
It can be configured as an A / D converter.

〔The invention's effect〕

As is apparent from the above description, according to the present invention, even when the emitter follower stage is not provided in the first stage of the comparator, the current flowing into the input electrode of one of the transistors when both transistors of the differential transistor pair are simultaneously turned on. A constant current source supplies a current approximately equal to the connection point of the plurality of resistors to compensate for the current flowing from the connection point of each resistor to the comparator, thereby reducing the non-linearity error of the input / output characteristics and the input signal. The error at the time of 1/2 input of the maximum level can be minimized.

Also, the constant current source supplied to the connection points of the plurality of resistors is:
It is not always necessary to provide them separately, and the same effect can be expected even if currents of adjacent connection points are supplied collectively.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a basic configuration of a parallel A / D converter of the present invention, FIGS. 2 to 8 are circuit diagrams of main parts used for describing the present invention, and FIG. 9 is a conventional parallel A / D converter. FIG. 2 is a block diagram illustrating an example of a type A / D converter. 8 ...... comparator 9 ...... input terminal 10 ...... gate circuit 11 ...... encoder Q _1, Q ₂ ...... first differential transistor pair Q _3, Q ₄ ...... second differential transistor pair Q _5, Q ₆ ... … The third differential transistor pair Q ₇ , Q ₈ … the fourth differential transistor pair Q ₉ , Q ₁₀ … the fifth differential transistor pair Q ₁₁ , Q ₁₂ … the sixth differential transistor pair Q ₁₃ , Q ₁₄ ...... seventh differential transistor pair P ₁ to P ₇ ...... connection point R ₁ to R ₈ ...... first to eighth resistor CC ₁ to CC ₇ ...... common current source CCS ₁ ～CCS ₇ ...... constant Current source

Claims (1)

(57) [Claims] An input signal is supplied to an input of one transistor, and a voltage at a connection point of the plurality of resistors is supplied as a reference voltage to an input of the other transistor. A comparator having a plurality of differential transistors, a gate circuit to which the output of the comparator is supplied, and an encoder to which the output of the gate circuit is supplied, when both transistors of the differential transistor are simultaneously turned on A parallel A / D converter, comprising: a constant current source that supplies a current substantially equal to a current flowing into an input of the one transistor to a connection point of the plurality of resistors.