JPS5851624A - Logical circuit - Google Patents

Abstract

PURPOSE:To decrease the number of transistors(TRs) of a circuit satisfying a plurality of logics, by providing a complementary P type logical circuit with a circuit viewing a reference potential from a specific node of an N type circuit of a complementary logical circuit consisting of P and N type TRs. CONSTITUTION:In series connecting a logical circuit 11 consisting of P type MOS Trs QPA-QPE and a logical circuit 12 consisting of N type MOSTRs QNA-QNE complementary with the circuit 11, when signals A-E of logics 1, 0 are applied to the gate of each TR, the 1st logic X=inversion (A.B+C.D.E) is outputted from a connecting point 14. In connecting a logical circuit 20 consisting of P type MOSTRs QPA''-QPE'' being the complementary relation with the circuit viewing the reference potential 16 from a connecting point 21 of the circuit 12 is connected between the connecting point 21 and a power supply 15, the 2nd logic Y=inversion (A.B.C.D+E) is outputted from the connecting point 21 to an output point 22. A complemetnary circuit consisting of a circuit viewing a reference potential, the circuits 11, 12 and 20, and a connecting point 21 are independently operated, and logics X, Y are outputted respectively to terminals 14 and 22 with less number of TRs.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a logic circuit, and relates to a nine logic circuit configured in a complementary manner using KN type and P type transistors.

Many types of logic circuits are used, but in recent years, logic circuits implemented as ICs have become mainstream. It is relatively easy to increase the degree of integration when configuring a logic circuit with a 1-mm IC, and the output power is relatively low regardless of whether the output is on or off.
Logic circuits configured in a complementary manner are often used for two reasons, such as the fact that the design of the next stage is easy due to the fact that the logic circuits can be easily designed.

FIG. 1 is a circuit diagram of a logic circuit constructed using a conventional C-MO8.

The logic circuit in this example consists of two/C/S/G type MO8 transistors Q and A that are assembled to satisfy a logic consisting of X-A-B+C-D.E (hereinafter referred to as the first logic). −
A P-type transistor/transistor circuit 11 based on Q
It consists of an N-type transistor/transistor circuit 12 made up of a performance-type MOβ transistor QNA"-QNI, and a
The register circuit 11 and the N-type transistor/register circuit 12 are connected in series between the power supply terminal 15 and the reference potential terminal 16, and are connected to the logic output terminal 14 for the node.
-E are P-type and N-type transistor circuits 11., respectively.
Transistors QPA to QFI in 12 # QNA −
The first logic 11X=A − is connected to the gate of QNIB.
A B+C-D-Et-satisfied through-phase type 1 logic circuit is constructed.

Now, if the amplitudes of "1" and "θ" indicating the states of logic inputs A and E are sufficient values for the power supply voltage E, a P-type transistor is Only either the circuit 11 or the N-type transistor/transistor circuit 12 is turned on, and the output terminal 14 K@1
Theory 11X-A @B+C.

It produces a "1" or "0" output that satisfies the relationship D-g.

Figure @2 is a circuit diagram of another example of the l1iii logic circuit configured with the conventional C-MO8.

This logic circuit has the same basic configuration as the logic circuit shown in FIG. 1, and has other logic (hereinafter @2
A complementary logic circuit that satisfies YxA, B, C, and D+E (referred to as the logic of / Only one of the transistor circuit 17 or the N-type transistor circuit 18 is turned on, and the second logic Y is output to the logic output terminal 19.
It produces an output that satisfies the relationship: =, =A, B・C・D−)−g.

Figure @3 is a diagram showing the relationship between logic inputs and logic outputs obtained in the logic circuits shown in Figures @1 and @2.

As explained above, the conventionally well-known complementary eyelid rotation WIIt
In order to construct a circuit that satisfies multiple logics for K, even if the type of logic is the same, K requires as many complementary logic circuits as the number of logics required, so K constructs a complementary logic circuit. The disadvantage is that the number of transistors required for Flt-4 increases proportionally to the number of logics.

SUMMARY OF THE INVENTION An object of the present invention is to provide a logic circuit that eliminates the above-mentioned drawbacks and reduces the number of transistors forming the logic circuit that satisfies a plurality of logics.

The logic circuit of the present invention includes a P-type transistor circuit including a plurality of N-type transistors and transistors, which are assembled to satisfy all logic requirements, and a P-type transistor circuit which is constructed to have a complementary relationship with the P-type transistor and transistor circuits. In a complementary logic circuit having a plurality of logic inputs, an N-type transistor circuit is provided and connected in series between a power supply and a reference potential point, and one logic output is obtained from the node. At least one of the logic inputs in J is a logic input, and a P-type or N-type transistor is assembled including a P-type or N-type transistor so as to satisfy another logic 81 different from the above-mentioned one logic. Shape logic circuit 1-
, is a reference potential (or a connection point between transistors included in the N-type or P-type transistor circuit assembled on the power supply side) when viewed from the node, and the reference potential (or power supply) @ is connected from the connection point. The circuit is connected between a power supply (or reference potential point) and a specific connection point whose circuit is complementary to the N-type or P-type logic circuit, and the other logic is connected from the specific connection point to the power supply (or reference potential point). The method is characterized in that it includes at least one means for obtaining a logical output that satisfies the following.

Next, embodiments of the present invention will be described in detail with reference to the drawings.

@4 Figure is a circuit diagram of an embodiment of the present invention.

The logic circuit of this embodiment is constructed to satisfy the first logic of X=A-B+C-D@B.
O8) A P-type transistor circuit 11 made up of transistors QPA to Q□, an N-type transistor circuit 12 assembled to have a complementary relationship with the transistor circuit 11, and Y-A
-B-C-D+B Enno/Smet/To type MO8) U/Jister QPA-~
It consists of a P-type logic circuit 20 based on the QPFi convention. The P-type transistor circuit 11 has a power supply terminal 15 and a reference potential terminal 1.
6, the P-type logic circuit 20 is connected in series with the transistor QNA" included in the N-type transistor/transistor circuit 12.
"" QNI A specific connection point 21 and power supply terminal 15 that is one connection point between each other and whose circuit when looking at the reference potential side from the connection point is complementary to the P-type logic circuit 20. The logic output terminal 14 is connected to the node between the P-type transistor circuit 11 and the N-type transistor circuit 12, and the logic output terminal 22 is connected to a specific connection point 21. are respectively QPA-Q□
#QNA~QNB# Connected to the even gates of Q and Aw~Q□, forming a complementary logic circuit that outputs logic outputs X and Yl.

Next, operation 4C) of the complementary logic circuit of this embodiment will be explained.

"1" indicates the state of logic power A-H applied to the gates of each transistor that constitutes the logic circuit.

If the amplitude of 0''' is a sufficient value for the power supply voltage E, the voltage between the drain and source of each transistor vD
s, is always E≧■D regardless of the operation of other transistors.
Since the relationship 0≧O is maintained, each transistor QPA controlled by the logic A-E = Ql”1!
The on/off operation of I QNA""' QNI I QPA"~Q□- is independent of the operation of other transistors. In a KPP type transistor, when the input becomes "1", it is always off, and the input becomes "0". On the other hand, in an N-type transistor, when the input is "1", it is always on, and when the input is "0", it is always off. Therefore,
P-type transistor/distor circuit 11. N-type transistor circuit 12
゜The four circuits of the P-type logic circuit 20 and the circuit connected to the reference potential side 1-+ from the specific connection point 21 are turned on and off in response to the combination of logic inputs A-hi, regardless of the operation of other circuits. Therefore, the result is a complementary circuit consisting of the P-type transistor circuit 11 and the N-type transistor circuit 12, and a complementary circuit consisting of the P-type logic circuit 20 and the reference potential side viewed from the specific connection point 21. Each circuit operates independently as a complementary logic circuit, and has logic inputs A-E.
Logic output terminals 14 and 22KX, respectively, according to the combination of
-A @B+C@D, E, y-r口bI5下〒E produces a logic output, and the relationship between the logic output and the logic power is determined by using two sets of conventionally known complementary logic circuits as shown in Figure 3. It is equal to the relationship in case.

As is clear from a comparison between FIGS. 1 and 2 and FIG. 4, according to the conventionally known logic circuits shown in FIGS.
In order to obtain an output that satisfies the second logic, 20 transistors were required, but according to the logic circuit of the embodiment shown in FIG. 4, a completely equivalent logic circuit is constructed with 15 transistors. Ru.

In the above embodiment, a logic circuit that satisfies the first logic is constructed by using a MO8 transistor/transistor, a KP type transistor on the power supply side, and a KN type transistor on the reference potential side. Construct a circuit that satisfies the second logic using Pi) transistors on the side, and find a complementary circuit to that circuit in an N-type sira/raster circuit that satisfies the first logic to satisfy @20 theory Blt'' Although the logic circuit was constructed, it is clear that the same effect can be obtained with a similar circuit configuration, even if it is not a transistor with similar characteristics.
Also, using an N-type transistor on the reference potential side, the 20th theory B
An equivalent logic circuit can also be constructed by constructing an N-type logic circuit that satisfies 11 and finding a complementary circuit to that circuit in a P-type transistor circuit that satisfies the first logic. Even if the circuit is constructed with N-type transistors and the circuit on the reference potential side is constructed with P-type transistors, a logic circuit with the same concept can be constructed by simply reversing the voltage polarity. Further, when configuring a logic circuit that requires third and fourth logics, the same idea can be extended.

As explained in detail above, the logic circuit of the present invention replaces some of the transistors necessary to configure the circuit satisfying the second theory 81 with the logic circuit necessary to satisfy the first theory 81. Since it is shared with the included transistors, it has the effect that the total number of transistors required to satisfy @1 and the second logic can be reduced by the number of shared transistors.

[Brief explanation of drawings]

Figure 1 is a circuit diagram of an example of a conventional logic circuit, Figure 2 is an enlarged circuit diagram of another example of a conventional logic circuit, and Figure 3 is a circuit diagram of another example of a conventional logic circuit.
FIG. 4 is a diagram showing the relationship between logic input and logic output obtained by the logic circuit shown in the figure, and is a circuit diagram of an embodiment of the present invention. 11...P-type transistor circuit, 12...
...N-type transistor/distor circuit, 14...Logic output terminal, 15...Power supply terminal, 16...Reference potential terminal% 17...P-type Converter/Jister circuit% 18...N type 2/Jister circuit, 19...
...Logic output terminal, 20...P-type logic circuit %21...Specific connection point, 22...Logic output terminal. Figure 1 Figure 2

Claims (1)

[Claims] A P-type transistor/transistor circuit comprising a plurality of N-type transistors and assembled to satisfy the following logic, and an N-type transistor circuit constructed to have a complementary relationship with the P-type transistor circuit. In a complementary logic circuit having a plurality of logic inputs, the circuit is connected in series between a power supply and a reference potential point, and is configured to obtain one logic output consisting of the nodes. At least −−) of the logic inputs are logic inputs,
KP so as to satisfy another logic different from the one logic above.
A P-type or N-type logic circuit assembled including P-type or N-type transistors is connected between transistors included in the N-type or P-type transistor circuit assembled on the reference potential (or power supply) side as viewed from the node. A specific connection point and a power supply (or from the specific connection point to the other potential point
- A logic circuit characterized in that it includes at least one means for obtaining a satisfactory logic output.