JPH0248821A - Logic circuit - Google Patents

Abstract

PURPOSE:To decrease the number of transistors(TRs) and to reduce the title circuit in scale and the power consumption by using a 1st TR of each individual logic circuit in common so as to apply respective processing. CONSTITUTION:The 1st TR of individual logic circuit 1A-1D is used in common to apply NAND logic between an input signal IC from a common input terminal TIC and results O1-O4 of NAND logic processing are outputted respectively from individual output terminals TO1-TO4. Then the 1st TR of individual logic circuits 1A-1D is used in common to reduce the number of TRs. Since the circuit scale is reduced, the current consumption is decreased. Moreover, the circuit above is applied to the circuit comprising 4 2-input NOR circuits whose one input in the two inputs is connected to the common input terminal TIC, then results O1-O4 of NOR processing are outputted from the individual output terminals TO1-TO4.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to logic circuits, and more particularly to logic circuits comprising a plurality of individual logic circuits having a common input terminal.

[Conventional technology]

An example of a conventional logic circuit of this type is shown in FIG. 3(a).

Shown in (b).

This logic circuit is composed of four individual logic circuits 2A to 2D having a two-person NAND circuit configuration, and each of the individual logic circuits 2A to 2D has a
The configuration is such that one input terminal of 2p is used as a common input terminal.

Each individual logic circuit 2A to 2D has a transistor Q.
ll~Q14. Q21～Q 241 Q 3x” Q
34°Q41 to Q44, each of which functions independently as a two-man NAND circuit.

[Problem to be solved by the invention]

The conventional logic circuit described above includes each individual logic circuit 2A to 2o.
However, since each circuit functions independently as a two-man NAND circuit, it has the drawback of increasing the number of transistors and increasing the circuit scale.
There is a drawback that the total sum of gate capacitance and drain capacitance increases, resulting in increased current consumption.

An object of the present invention is to provide a logic circuit that can reduce the circuit scale and reduce current consumption.

[Means to solve the problem]

The logic circuit of the present invention includes a first transistor of one conductivity type whose source is connected to a first power supply terminal and whose gate is connected to a common input terminal, and between the drain of this first transistor and an individual output terminal. at least one second transistor of one conductivity type connected to and having its gate connected to the individual input terminal, complementary to the first and second transistors between the individual output terminal and a second power supply terminal; said first transistor, each comprising a third transistor of a reverse conductivity type connected to the common input terminal and having a gate connected to said common input terminal, and at least one fourth transistor of a reverse conductivity type having a gate connected to said individual input terminal. It also has a plurality of individual logic circuits each of which performs predetermined logic processing.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

In this embodiment, one of the two human forces is connected to the common input terminal T.
It consists of four two-way NAND circuits connected to Ic.

The N-type transistor Ql has a source connected to the first power supply terminal Tss (power supply voltage Vss), and a gate connected to the common input terminal TIc (input signal Ic).

The individual logic circuits 18 to ID have gates connected to each individual input terminal T.
N-type second transistors Q12 respectively connected to the drains of the first transistor Q1 and the individual output terminals To1 to TO4;
A first transistor Q1 and each second transistor Q12 to Q are connected between ~Q42, each individual output terminal To, ~TO4, and a second power supply terminal Too (power supply voltage ■DD).
P-type third transistors Q13~ connected in a complementary manner to 42 and having their gates connected to the common input terminal;
Q43 and gate to each individual input terminal T1. ~T1. P-type fourth transistors Qla to Q44 are connected to the transistors Qla to Q44, respectively, and together with the first transistor Ql,
It is configured to perform manual NAND processing.

That is, each of the individual logic circuits I8 to 1r) shares the first transistor Q+ to receive an input signal IC from the common input terminal TIC and an input signal 1. - Performs NAND processing with I4, and outputs the NAND processing results from each individual output terminal To, ~T04 (
01 to o4).

In this way, by sharing the first transistor Qt in each of the individual logic circuits IA to ID, the number of transistors can be reduced, so the circuit scale can be reduced and current consumption can be reduced. Can be done.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention.

In this embodiment, one of the two human forces is connected to the common input terminal T.
This is applied to four two-person NOR circuit configuration circuits connected to Ic.

Each of the individual logic circuits 1i to 1)I shares the first transistor Q1 and has a common input terminal TI.

Input signals from IC and each individual input terminal T1. NOR processing is performed with the input signals 11 to 4 from T-4, and the NOR processing results (01 to 04) are output from the individual ratio output terminals TO1 to To4.

〔Effect of the invention〕

As explained above, the present invention has a configuration in which each individual logic circuit shares the first transistor to perform respective logic processing, thereby reducing the number of transistors. This has the effect of reducing power consumption.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 and FIG. 2 are circuit diagrams showing first and second embodiments of the present invention, respectively, and FIG. 3 (a). (b) is a transistor level circuit diagram and a logic symbol level circuit diagram showing an example of a conventional logic circuit, respectively. IA~LM, 2A~2o-individual logic circuit, QIQ+1~
Q24・Q21～Q24・Q31～Q34・Q41～Q
44...Transistor. direction million map

Claims (1)

[Claims] a first transistor of one conductivity type whose source is connected to the first power supply terminal and whose gate is connected to the common input terminal; and the first transistor is connected between the drain of the first transistor and the individual output terminal and whose gate is connected to the individual input terminal at least one second transistor of one conductivity type connected to the terminal; connected complementary to the first and second transistors between the individual output terminal and the second power supply terminal; A third transistor of a reverse conductivity type connected to the common input terminal, and at least one fourth transistor of a reverse conductivity type whose gate is connected to the individual input terminal, respectively, each of which performs a predetermined logic process together with the first transistor. A logic circuit comprising a plurality of individual logic circuits.