JPH0248821A - Logic circuit - Google Patents

Logic circuit

Info

Publication number
JPH0248821A
JPH0248821A JP63200508A JP20050888A JPH0248821A JP H0248821 A JPH0248821 A JP H0248821A JP 63200508 A JP63200508 A JP 63200508A JP 20050888 A JP20050888 A JP 20050888A JP H0248821 A JPH0248821 A JP H0248821A
Authority
JP
Japan
Prior art keywords
individual
transistor
circuit
input terminal
common
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63200508A
Other languages
Japanese (ja)
Inventor
Akira Yazawa
矢沢 晃
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP63200508A priority Critical patent/JPH0248821A/en
Publication of JPH0248821A publication Critical patent/JPH0248821A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To decrease the number of transistors(TRs) and to reduce the title circuit in scale and the power consumption by using a 1st TR of each individual logic circuit in common so as to apply respective processing. CONSTITUTION:The 1st TR of individual logic circuit 1A-1D is used in common to apply NAND logic between an input signal IC from a common input terminal TIC and results O1-O4 of NAND logic processing are outputted respectively from individual output terminals TO1-TO4. Then the 1st TR of individual logic circuits 1A-1D is used in common to reduce the number of TRs. Since the circuit scale is reduced, the current consumption is decreased. Moreover, the circuit above is applied to the circuit comprising 4 2-input NOR circuits whose one input in the two inputs is connected to the common input terminal TIC, then results O1-O4 of NOR processing are outputted from the individual output terminals TO1-TO4.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は論理回路に関し、特に共通の入力端子をもつ複
数の個別論理回路を備えた論理回路に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to logic circuits, and more particularly to logic circuits comprising a plurality of individual logic circuits having a common input terminal.

〔従来の技術〕[Conventional technology]

従来この種の論理回路の一例を第3図(a)。 An example of a conventional logic circuit of this type is shown in FIG. 3(a).

(b)に示す。Shown in (b).

この論理回路は、4つの2人力NAND回路構成の個別
論理回路2A〜2Dで構成され、各個別論理回路2A〜
2pの一方の入力端子を共通入力端子とした構成となっ
ている。
This logic circuit is composed of four individual logic circuits 2A to 2D having a two-person NAND circuit configuration, and each of the individual logic circuits 2A to 2D has a
The configuration is such that one input terminal of 2p is used as a common input terminal.

各個別論理回路2A〜2Dは、それぞれトランジスタQ
ll〜Q14.Q21〜Q 241 Q 3x” Q 
34゜Q41〜Q44を備え、それぞれ独立して2人力
NAND回路としての機能をはなす構成となっている。
Each individual logic circuit 2A to 2D has a transistor Q.
ll~Q14. Q21~Q 241 Q 3x” Q
34°Q41 to Q44, each of which functions independently as a two-man NAND circuit.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の論理回路は、各個別論理回路2A〜2o
が、それぞれ独立して2人力NAND回路としての機能
をはなす構成となっているので、トランジスタ数が多く
なり、回路規模が大きくなるという欠点があり、また、
ゲート容量及びドレイン容量の総和が大きくなり消費電
流が増大するという欠点がある。
The conventional logic circuit described above includes each individual logic circuit 2A to 2o.
However, since each circuit functions independently as a two-man NAND circuit, it has the drawback of increasing the number of transistors and increasing the circuit scale.
There is a drawback that the total sum of gate capacitance and drain capacitance increases, resulting in increased current consumption.

本発明の目的は、回路規模を縮減しかつ消費電流を低減
することができる論理回路を提供することにある。
An object of the present invention is to provide a logic circuit that can reduce the circuit scale and reduce current consumption.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の論理回路は、ソースを第1の電源供給端子と接
続しゲートを共通入力端子と接続する一導電型の第1の
トランジスタと、この第1のトランジスタのドレインと
個別出力端子との間に接続されゲートを個別入力端子と
接続する一導電型の少なくとも1つの第2のトランジス
タ、前記個別出力端子と第2の電源供給端子との間に前
記第1及び第2のトランジスタに対して相補型に接続さ
れ、ゲートを前記共通入力端子と接続する逆導電型の第
3のトランジスタ及びゲートを個別入力端子と接続する
少なくとも1つの逆導電型の第4のトランジスタをそれ
ぞれ備え前記第1のトランジスタと共にそれぞれ所定の
論理処理をする複数の個別論理回路とを有している。
The logic circuit of the present invention includes a first transistor of one conductivity type whose source is connected to a first power supply terminal and whose gate is connected to a common input terminal, and between the drain of this first transistor and an individual output terminal. at least one second transistor of one conductivity type connected to and having its gate connected to the individual input terminal, complementary to the first and second transistors between the individual output terminal and a second power supply terminal; said first transistor, each comprising a third transistor of a reverse conductivity type connected to the common input terminal and having a gate connected to said common input terminal, and at least one fourth transistor of a reverse conductivity type having a gate connected to said individual input terminal. It also has a plurality of individual logic circuits each of which performs predetermined logic processing.

〔実施例〕〔Example〕

次に、本発明の実施例について図面を参照して説明する
Next, embodiments of the present invention will be described with reference to the drawings.

第1図は本発明の第1の実施例を示す回路図である。FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

この実施例は、2人力のうち1人力を共通入力端子T 
I cと接続する4つの2人力NAND回路で構成され
ている。
In this embodiment, one of the two human forces is connected to the common input terminal T.
It consists of four two-way NAND circuits connected to Ic.

N型のトランジスタQlは、ソースを第1の電源供給端
子Tss(電源電圧Vss)と接続し、ゲートを共通入
力端子TIc (入力信号Ic)と接続している。
The N-type transistor Ql has a source connected to the first power supply terminal Tss (power supply voltage Vss), and a gate connected to the common input terminal TIc (input signal Ic).

個別論理回路1八〜IDは、ゲートを各個別入力端子T
11〜T I aとそれぞれ接続し、第1のトランジス
タQ1のドレインと各個別出力端子To1〜TO4との
間にそれぞれ接続されたN型第2のトランジスタQ12
〜Q42と、各個別出力端子To、〜TO4と第2の電
源供給端子Too(電源電圧■DD)との間に、第1の
トランジスタQ1及び各第2のトランジスタQ12〜Q
42に対してそれぞれ相補型に接続され、ゲートを共通
入力端子と接続するP型の第3のトランジスタQ13〜
Q43及びゲートを各個別入力端子T1.〜T1.と接
続するP型の第4のトランジスタQla〜Q44とをそ
れぞれ備え、第1のトランジスタQlと共にそれぞれ2
人力NAND処理を行う構成となっている。
The individual logic circuits 18 to ID have gates connected to each individual input terminal T.
N-type second transistors Q12 respectively connected to the drains of the first transistor Q1 and the individual output terminals To1 to TO4;
A first transistor Q1 and each second transistor Q12 to Q are connected between ~Q42, each individual output terminal To, ~TO4, and a second power supply terminal Too (power supply voltage ■DD).
P-type third transistors Q13~ connected in a complementary manner to 42 and having their gates connected to the common input terminal;
Q43 and gate to each individual input terminal T1. ~T1. P-type fourth transistors Qla to Q44 are connected to the transistors Qla to Q44, respectively, and together with the first transistor Ql,
It is configured to perform manual NAND processing.

即ち、各個別論理回路I八〜1r)は、第1のトランジ
スタQ+をそれぞれ共用して共通入力端子TICからの
入力信号ICと各個別入力端子TI、〜T■4からの入
力信号1.−I4とのNAND処理を行い、各個別出力
端子To、〜T04からそれぞれのNAND処理結果(
01〜o4)を出力する構成となっている。
That is, each of the individual logic circuits I8 to 1r) shares the first transistor Q+ to receive an input signal IC from the common input terminal TIC and an input signal 1. - Performs NAND processing with I4, and outputs the NAND processing results from each individual output terminal To, ~T04 (
01 to o4).

このように、各個別論理回路IA〜IDで第1のトラン
ジスタQtを共有することにより、トランジスタの数を
低減することができるので、回路規模を縮減することが
でき、また消費電流を低減することができる。
In this way, by sharing the first transistor Qt in each of the individual logic circuits IA to ID, the number of transistors can be reduced, so the circuit scale can be reduced and current consumption can be reduced. Can be done.

第2図は本発明の第2の実施例を示す回路図である。FIG. 2 is a circuit diagram showing a second embodiment of the present invention.

この実施例は、2人力のうち1人力を共通入力端子T 
I cと接続する4つの2人力NOR回路構成の回路に
適用したものである。
In this embodiment, one of the two human forces is connected to the common input terminal T.
This is applied to four two-person NOR circuit configuration circuits connected to Ic.

各個別論理回路1i〜1)Iは、それぞれ第1のトラン
ジスタQ1を共用して共通入力端子TI。
Each of the individual logic circuits 1i to 1)I shares the first transistor Q1 and has a common input terminal TI.

からの入力信号ICと各個別入力端子T1.〜T工4か
らの入力信号11〜工、とのNOR処理を行い、各個別
比出力端子TO1〜To4からそれぞれのNOR処理結
果(01〜04)を出力構成となっている。
Input signals from IC and each individual input terminal T1. NOR processing is performed with the input signals 11 to 4 from T-4, and the NOR processing results (01 to 04) are output from the individual ratio output terminals TO1 to To4.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、各個別論理回路で第1の
トランジスタを共用してそれぞれの論理処理を行う構成
とすることにより、トランジスタの数を低減することが
できるので、回路規模の縮減及び消費電力の低減をはか
ることができる効果がある。
As explained above, the present invention has a configuration in which each individual logic circuit shares the first transistor to perform respective logic processing, thereby reducing the number of transistors. This has the effect of reducing power consumption.

【図面の簡単な説明】 第1図及び第2図はそれぞれ本発明の第1及び第2の実
施例を示す回路図、第3図(a)。 (b)はそれぞれ従来の論理回路の一例を示すトランジ
スタレベルの回路図及び論理シンボルレベルの回路図で
ある。 IA〜LM、2A〜2o−個別論理回路、QIQ+1〜
Q24・Q21〜Q24・Q31〜Q34・Q41〜Q
44・・・トランジスタ。 方 図 万 図
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 and FIG. 2 are circuit diagrams showing first and second embodiments of the present invention, respectively, and FIG. 3 (a). (b) is a transistor level circuit diagram and a logic symbol level circuit diagram showing an example of a conventional logic circuit, respectively. IA~LM, 2A~2o-individual logic circuit, QIQ+1~
Q24・Q21~Q24・Q31~Q34・Q41~Q
44...Transistor. direction million map

Claims (1)

【特許請求の範囲】[Claims] ソースを第1の電源供給端子と接続しゲートを共通入力
端子と接続する一導電型の第1のトランジスタと、この
第1のトランジスタのドレインと個別出力端子との間に
接続されゲートを個別入力端子と接続する一導電型の少
なくとも1つの第2のトランジスタ、前記個別出力端子
と第2の電源供給端子との間に前記第1及び第2のトラ
ンジスタに対して相補型に接続され、ゲートを前記共通
入力端子と接続する逆導電型の第3のトランジスタ及び
ゲートを個別入力端子と接続する少なくとも1つの逆導
電型の第4のトランジスタをそれぞれ備え前記第1のト
ランジスタと共にそれぞれ所定の論理処理をする複数の
個別論理回路とを有することを特徴とする論理回路。
a first transistor of one conductivity type whose source is connected to the first power supply terminal and whose gate is connected to the common input terminal; and the first transistor is connected between the drain of the first transistor and the individual output terminal and whose gate is connected to the individual input terminal at least one second transistor of one conductivity type connected to the terminal; connected complementary to the first and second transistors between the individual output terminal and the second power supply terminal; A third transistor of a reverse conductivity type connected to the common input terminal, and at least one fourth transistor of a reverse conductivity type whose gate is connected to the individual input terminal, respectively, each of which performs a predetermined logic process together with the first transistor. A logic circuit comprising a plurality of individual logic circuits.
JP63200508A 1988-08-10 1988-08-10 Logic circuit Pending JPH0248821A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63200508A JPH0248821A (en) 1988-08-10 1988-08-10 Logic circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63200508A JPH0248821A (en) 1988-08-10 1988-08-10 Logic circuit

Publications (1)

Publication Number Publication Date
JPH0248821A true JPH0248821A (en) 1990-02-19

Family

ID=16425478

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63200508A Pending JPH0248821A (en) 1988-08-10 1988-08-10 Logic circuit

Country Status (1)

Country Link
JP (1) JPH0248821A (en)

Similar Documents

Publication Publication Date Title
US4749886A (en) Reduced parallel EXCLUSIVE or and EXCLUSIVE NOR gate
Sheikholeslami et al. Look-up tables (LUTs) for multiple-valued, combinational logic
JPH0248821A (en) Logic circuit
JPS5823010B2 (en) differential amplifier device
US5994936A (en) RS flip-flop with enable inputs
JPS60198922A (en) Mosfet circuit
JPH03132115A (en) Semiconductor integrated circuit
JPS5922435A (en) Latch circuit
JPS5931253B2 (en) MISFET logic circuit with depletion type load transistor
US3678290A (en) Ratioless and non-inverting logic circuit using field effect boosting devices
JP2830244B2 (en) Tri-state buffer circuit
JPS594890B2 (en) digital circuit
CA1109128A (en) Ternary logic circuits with cmos integrated circuits
JP2734531B2 (en) Logic circuit
DE59510811D1 (en) METHOD FOR SWITCHING HIGHER VOLTAGES ON A SEMICONDUCTOR CHIP
JPH03280294A (en) Memory cell circuit for semiconductor integrated circuit device
JPH0638491Y2 (en) Delay circuit
JPS63283315A (en) Output buffer circuit
JPS62188421A (en) Input circuit
JPS6159012B2 (en)
JPS61224623A (en) Complementary gate circuit
JP3073064B2 (en) Multi-input logic circuit and semiconductor memory
JPH01209814A (en) Semiconductor integrated circuit
JPS6096914A (en) Flip-flop circuit
JPH08116252A (en) Exclusive or circuit and not circuit for exclusive or