JPH01180107A - Bias generating circuit - Google Patents

Abstract

PURPOSE:To allow the circuit to follow the fluctuation of an optimum bias voltage of a differential type inverter circuit attended with the temperature change of an IC chip by using a bias generating circuit provided with a differential circuit and a source follower type buffer circuit. CONSTITUTION:A drain terminal of differential pair FETs 1, 2 is connected to a power supply VDD via load resistors 3, 4 and a level shifter. Moreover, the gate of source follower FETs 7, 8 in pairs is connected to each drain of the FETs 1, 2 and each source is connected to ground via level shifters 9, 10 and constant current sources 11, 12. Furthermore, a high resistance 13 is inserted between a connecting point N1 between the level shift 9 and the constant current source 11 and a connecting node N2 between the level shifter 10 and the constant current source 12, a neutral point of the high resistance 13 is connected to ground by a bias capacitor 14 and a bias voltage is outputted from the neutral point via a high resistance 15. Since the neutral point of the high resistance 13 is always at a designed bias, the circuit follows the fluctuation of the optimum bias voltage due to the temperature change in the differential inverter circuit 16.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a bias generation circuit, and in particular to bias generation circuits for differential circuits using FETs as basic elements and differential inverter circuits using source follower type buffer circuits as basic circuits. Regarding generation circuits.

[Conventional technology]

Conventionally, this type of bias generation circuit, as shown in FIG. 3, generates a bias voltage for the differential inverter circuit 16 using a high resistor 20.
1 through a high resistance 22.

[Problem that the invention seeks to solve]

The conventional bias generation circuit described above generates the bias voltage by resistor division, so the voltage is always constant regardless of the temperature change of the IC chip, making it ideal for a differential inverter circuit that responds to temperature changes in the characteristics of FETs and diodes. The disadvantage is that it cannot follow changes in bias voltage.

The object of the present invention is to
It is an object of the present invention to provide a bias generation circuit that can follow changes in the optimum bias voltage of a differential inverter circuit corresponding to changes in diode characteristics.

[Means for solving problems]

The bias generation circuit of the present invention has a pair of drains connected from the first level shifter to the power supply terminal via respective load resistors, and a common source connected to the ground terminal via the first constant current source. a differential circuit comprising a first and a second FET, and a gate of each of the first and second FETs;
a pair of FETs, the drains of which are connected to the power supply terminal, and the sources of which are connected to the ground terminal via second and third level shifters and second and third constant current sources, respectively. A connection node between the second level shifter and the second constant current source is connected to the gate of the second FET, and a connection node between the third level shifter and the third constant current source is connected to the gate of the second FET. The second connection node is the first connection node.
A source follower type buffer circuit connected to the gate of the FET, and a high resistor inserted between the first node and the second node and outputting a bias voltage from the midpoint thereof.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram of a first embodiment of the present invention.

Ru.

As shown in FIG.
, 4 are connected, and the other ends of the load resistors 3 and 4 are connected to the power supply VDD via a first level shifter 5. Further, the common sources of the differential pairs FETI and FETI 2 are grounded via the first constant current source 6 to form a differential circuit.

The respective gates of the source follower FETs 7 and 8 as the third and fourth FETs in the pair are connected to the respective drains of the differential pair FETs I and 2, the drains are connected to the power supply VDD, and the respective sources are connected to the second and third level shifters 9 and 10 and second and third constant current sources 11
and 12 to ground. Further, the first connection node N between the level shifter 9 and the constant current source 11 is connected to the gate of the differential pair FET2, and the second connection node N2 between the level shifter 10 and the constant current source 12 is connected to the gate of the differential pair FET I. A source follower type buffer circuit is configured by connecting to the gate.

A high resistance 13 is inserted between connection nodes N1 and N2, the middle point of the high resistance 13 is grounded by a bypass capacitor 14, and a bias voltage is output from the middle point via the high resistance 15.

With this configuration, the connection node N.

The potentials of N2 and N2 are one high level and the other low level, and the midpoint of the high resistance 13 always becomes the design bias voltage. It is possible to follow the fluctuation of the optimum bias voltage for.

FIG. 2 is a circuit diagram of a second embodiment of the invention.

As shown in FIG. 2, the second embodiment is a circuit in which one-stage differential pair FETs 17 and 18 are further connected in cascade to the differential pairs FETI and 2 of the differential circuit of the first embodiment. Similarly, the case where the differential pair F'ET of the differential inverter circuit 19 is increased by one stage can be accommodated.

〔Effect of the invention〕

As explained above, the present invention uses a bias generation circuit that includes a differential circuit and a source follower type buffer circuit, thereby making it possible to change the optimum bias voltage of a differential inverter circuit with the same configuration due to temperature changes of an IC chip. This has the effect of generating a bias voltage that follows.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a first embodiment of the present invention, FIG. 2 is a circuit diagram of a second embodiment of the present invention, and FIG. 3 is a circuit diagram of an example of a conventional bias generation circuit. 1.2...Differential pair FET, 3.4...Load resistance, 5
．． 9.10... Level shifter, 7,8... Source follower FET, 6,11.12... Constant current source, 13.
15, 20, 21.22...High resistance, 14...Bypass capacitor, 16.19...Differential inverter circuit.

Claims (1)

[Claims] a pair of first and second FETs whose respective drains are connected from the first level shifter to the power supply terminal via respective load resistors and whose common sources are connected to the ground terminal via the first constant current source; a differential circuit comprising a differential circuit having respective gates connected to the drains of the first and second FETs, drains connected to the power supply terminal, and respective sources connected to second and third level shifters and second and third FETs, respectively;
The third of the pair is connected to the ground terminal through a constant current source of
and a fourth FET, the second level shifter and the second
A connection node between the third level shifter and the third constant current source is connected to the gate of the second FET, and a second connection node between the third level shifter and the third constant current source is connected to the gate of the first FET. A bias generation circuit comprising a source follower type buffer circuit and a high resistance inserted between the first node and the second node and outputting a bias voltage from the midpoint thereof.