JPS60116222A - Selector circuit - Google Patents

Abstract

PURPOSE:To decrease the semiconductor chip area by using a complementary MOS transistor (TR) so as to make one TR correspond to one data input and switching complementarily the TR with a selection signal at the same level. CONSTITUTION:Drains of an N-channel MOSTR10 and a P-channel MOSTR12 are respectively connected to the 1st input terminal IN1 and the 2nd input terminal IN2 and the sources of the TRs 10, 12 are connected to an output terminal OUT3. A selection input S is applied to the gates of the TRs 10, 12. When the input S is at an H level, a data input IN1 is transmitted to a terminal 3 and when the input S is at L level, the input IN2 is transmitted to the terminal 3. Thus, the number of TRs and the number of input terminals for selection signals are decreased and in forming the TRs on a semiconductor substrate, the semiconductor chip area is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] The present invention relates to a selector circuit, and relates to a selector circuit using 1% complementary MOS transistors.

[Prior art]

Conventionally, as shown in FIG.
8) Transistor 10.11 and P-type MOS transistor 1
2.13 They were connected in parallel as shown in the figure, and selection signals S and S of opposite logic levels were input to both to turn them on and off, thereby fulfilling the selector function. Therefore, when trying to select the two data inputs INI and IN2, the following 9. N type MO8 transistor 10, 11
and P-type MOS transistors 12 and 13, two MOS) transistors and two selection signal input terminals 4).
5 was required.

Therefore, when attempting to implement the above-mentioned selector circuit on a semiconductor substrate, there is a drawback that the number of transistors and the number of selection signal input terminals are large, resulting in a large area.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a selector circuit which can eliminate the above drawbacks, reduce the number of transistors and selection signal input terminals, and reduce the area of a semiconductor chip when integrated on a semiconductor substrate.

[Structure of the invention]

The selector circuit of the present invention includes an N-type MO8) transistor whose drain is connected to a first data input terminal, whose source is connected to an output terminal, and whose gate is connected to a selection input terminal, and whose drain is connected to a second data input terminal. The source is the N-type MO
A P-type MO transistor (8) transistor whose source is connected to the output terminal of the S transistor and whose gate is connected to the selection input terminal together with the gate of the N-type MOS transistor.

That is, the selector circuit of the present invention uses complementary MOS transistors, one transistor corresponds to one data input, and even selection signals of the same level are switched in a complementary manner to achieve the selector function. The selection signal is also increased, resulting in a reduction in the number of transistors and the number of selection signal input terminals.

[Explanation of Examples]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 2 is a circuit diagram of one embodiment of the present invention.

This embodiment consists of an N-type MO transistor 10 whose drain is connected to a first data input terminal l, whose source is connected to an output terminal 3 and whose gate is connected to a selection input terminal 4, and whose drain is connected to a second data input terminal 1. 2 and the source is N type MO8
) A P-type MOS transistor 12 whose gate is connected to the output terminal 3 together with the source of the transistor 1o and whose gate is connected to the selection input terminal S together with the gate of the N-type MOS transistor 10. First and second data input terminals1.
2 respectively have first and second data input signals IN, .
IN2 is input, and selection signal S is input to selection signal input terminal 4.
is input. Table 1 is a truth table of the selector function of this embodiment.

This table is written using positive logic.

When the selected human power S is 11", that is, high potential, the output OUT
The first data input INI is transmitted to 10w1, and conversely 10w1
That is, when the potential is low, the second data input IN2 is transmitted. However, in terms of the first data value at the output OUT, it is 11'' from the first data input INi.

1 from the second data input IN2 when transmitting 10W information
1@, it is different from the time of I01 information transmission. The information transmission situation will be explained using waveform diagrams.

FIG. 3 is a waveform diagram of voltages appearing at each terminal of the embodiment shown in FIG. 2 and the applied example shown in FIGS. 4 and 5. Third
The figure shows changes in voltage waveforms corresponding to states 1, 2, and 3.4 in Table 1.

If the input voltage amplitude of data inputs INI and IN2 is VD, then in state 1, that is, when the 111 information of data input INI is transmitted to the output OUT through the N-type MO8) transistor, the potential of the selection input S is the voltage of the 9N-type MOS transistor. The voltage decreases by the threshold voltage VTN.

Conversely, in state 4, when the 101 information of the data input IN2 is transmitted to the output α through the P-type MO transistor 8), the potential of the selection signal S increases by the threshold voltage IVTPI of the 5p-type MOS transistor.

However, it is easy to understand that if the threshold voltage of the next-stage inverter to which the output OUT is input is appropriately set and amplified, the original amplitude VD can be restored.

FIG. 4 is a circuit diagram of a first application example of the present invention.

An inverter 4 is connected to the selector circuit 30 of the present invention shown in FIG.
The inverter 40 is a normal CMOS inverter in which an N-type MO8) transistor 20 and a P-type MOS transistor 22 are connected. The voltage waveform of the output INV-OUT of the inverter 40 is shown in FIG. By connecting the inverter 4o, the voltage amplitude of 9INV·OUT becomes the original amplitude VD.

FIG. 5 is a circuit diagram of a second application example of the present invention.

This is an MO in series with the inverter 40 of the circuit shown in FIG.
A resistor formed by S transistors 21 and 23 is connected.

As shown in Figure 3, the voltage at the output OUT is V in state l.
It is shifted by TN and by IVTPI in state 4. This shift causes the P-type MO8 of the inverter 40 to
) Both the transistor 22 and the N-type MOS transistor 20 are turned on, and a through current flows.

By connecting MOS transistors 21 and 23 of the same conductivity type to both MO8 transistors 20 and 22 of the inverter 40 to form a resistor, the through current flowing through the inverter 30 can be reduced. Output INV-OUT
has the same waveform as INV-OUT shown in FIG.

〔Effect of the invention〕

As described in detail above, according to the present invention, a selector circuit can be obtained that can reduce the number of transistors and selection signal input terminals and reduce the area of a semiconductor chip when integrated on a semiconductor.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an example of a conventional selector circuit, FIG. 2 is a circuit diagram of an embodiment of the present invention, and FIG. 3 is a circuit diagram of an embodiment shown in FIG. 2, and FIGS. 4 and 5. 4 and 5 are circuit diagrams of the first and second application examples of the present invention. 1.2... Data input terminal, 3... Output terminal, 4, Death... Selection input terminal, 6...
・Inverter output terminals, 10, 11, 20, 21
...N-type MO8) transistor, 12.13,2
2.23...P-type MO8) transistor, 30.
...Selector circuit, 40...Inverter, INI, IN2...Data input, INV・O
UT...Inverter output, OUT...
Output, S, S...Selection signal. Mei 4 illustration, 5 Wa cooking @, S-7 → I → su ÷ 4-1 Atsushi 3 illustration

Claims (1)

[Claims] N-type MO whose drain is connected to the first data input terminal, whose source is connected to the output terminal, and whose gate is connected to the selection input terminal
an S transistor; a P-type MO8 having a drain connected to a second data input terminal, a source connected to the output terminal together with the source of the N-type MOS transistor, and a gate connected to the selection input terminal together with the gate of the N-type MOS transistor;
) A selector circuit comprising a transistor.