JPS5851617A - Parallel-serial conversion system - Google Patents

Abstract

PURPOSE:To convert parallel data into serial data with simple circuit constitution, by constituting the system with a shift register having a bit number more than the bit number to be converted by one bit and a decoder. CONSTITUTION:A parallel-serial conversion circuit of n bits consists of a shift register 11 having (n+1) sets of FFs 1-(n+1) and a decoder 12. A load signal is energized with a start pulse phi2, parallel data is set to the FF(n+1) from the FF2 and 1 is set to the FF1. Next, the state of each FF is sequentially shifted right with a data transfer clock phi1, and data are outputted as serial data from the FF(n+1), and when the parallel data are converted all into the serial data, the decoder 12 outputs the load signal. 1 is set again to the FF1 with the load signal and the parallel data are set to the FF(n+1) from the FF2, and the parallel-serial conversion is repeated at each parallel data length with the clock phi1 similarly.

Description

[Detailed description of the invention] Regarding the zero-start @Tate parallel series exchange system.

Conventionally, the method of converting parallel data into single column data is l1
11fc, it consisted of a shift register 1, a bit counter 2, and a decoder 5. The input parallel data is sent to the shift register 1 according to the L axis 4 signals.
The data is input to the 7th flip flop 〃4 (4 1.2, fist, attack), and the data is transferred to the right side by the data transfer, and output as flip 70 flop 〃duck or b serial data. . That is, the bit counter 2 &: counts the number of data transfers, and the output is sent to the decoder lc to determine when all the parallel data has been folded, and sequentially converts the next parallel data into serial data. The common method was to convert it into Therefore, in the conventional system, shift registers, bit counters, and decoders are essential.63. Practical E:lll required a corresponding weight product and weight.

C for the removal of the bit counter that applies to the above-mentioned Juto Technique under Honmari Akira? '＠Top with what was left, □Therefore, Motoyaaki's ■fishing is to increase the shift register by 1 bit and make 1 pit F.
Parallel data can be converted to serial data with a simpler en* configuration that does not require a counter.
! To provide a parallel-to-serial conversion method.

The first point above for Honyakan is the number of bits to be converted (data length)
By the configuration of the shift register with 1 bit more than 1 bit and the decoder, each of the 7 bits in the shift register (however, the 7 bits can be output as serial data at the same time as the input)
(excluding Ritsubufutsubu) is always input to the Yaki decoder, recognizes the specific pattern that appears when all the Yaki decoder parallel data is converted to serial data, and inputs the next parallel data to the shift register, 1. This is achieved by converting the data into parallel and serial data in sequence.

Hereinafter, with reference to FIG. 112, the parallel-to-serial conversion method according to the present invention will be explained in detail as a preferred embodiment of a platform for performing parallel-to-serial conversion of a certain bit length. In the embodiment, a shift register 11 having (s+1) blocks and a decoder 12 are combined, and 1 to S
The signal Ila representing the state of each of the flip-flops F11 to F1 is sent to the decoder 12, and the output of the decoder is configured to be an input to the shift register 11's Leajl1 and the flip-flop 70 to the flip-flop FF1. .

The first parallel data is the start pulse llI
Lead 1 is activated by Jin inputting 2,
FF (% + 1) &: is set from the 7tl knob FF2, and 11 binding is set to the 7th divided by the FF1. [lchi, Schiff) Takeover in register 11 + 1 7 Lipfu Sotsubu JF71 % FF (s+1) t! F
FI or 67FJF(s+1)t sequentially IXXX・*a*
xxx (No. II × is the state of each bit of parallel data"
In the state of 10" or @11", the state of 70" or 11" is shifted to the right, and the state of each 7 lip is shifted to the right, and the result is a double flop. ! ! (Run+1) or bI serial data and output, IIkml of shift register 11 is (10001'-
When the state of @01X is reached, that is, when all the parallel data has been converted to serial data, the decoder 12
Outputs the d symbol. This (, a @ d command, 7 Ritsubufutsubu IF1 &: is 1" again,]] 1 Tsubufutsubu JFJF or 77' (s + 1) c is a parallel data dragon, and the following data transfer is similarly locked * IE : Therefore, the parallel data length *C* arrangment conversion is <return.

Therefore, according to the present invention, by adding just one comparison flip 70 to the conventional parallel-to-serial conversion method, the bit shift ψ
Completely remove the elements, and make it to J1 on a smaller scale!
The VH5 effect will occur if the same treatment as before is possible.

Above, we have explained a good example of this beak,
It is merely an illustrative example and the basis of the present application is limited by the described embodiments, so 'Ikv'
Of course.

[Brief explanation of the drawing]

1111! Configuration W of the parallel-to-serial conversion method by Shajoto, a configuration showing an example of the parallel-to-serial conversion method by No. 2m Company Hon 11@
It is. 1- ・Fist S/7) 1/9 star 121 ・Bi-sit counter 13 ・・Rumor meeting゛@+-tekose 9'', 11・Reisan shift shift 9 nuta, 12@11 fan de-da,〃(( (Full 1.2
,・Lu...S) ψLu Fist Flip 7 Kentsubu, f...Fist Data Transfer? Row 5F#, 11 I pin/data transfer 4I-Ivy, Shin 2 fist--Start pulse

Claims (1)

[Claims] For conversion from parallel data to serial data, it is equipped with a shift register whose number of bits is p1 bits more than the number of bits to be converted (data length), and a decoder, and each of the 7 lips in the shift register has 70 bits. By inputting the state of &: into the decoder, the decoder recognizes a specific pattern that appears when all parallel data is converted to serial data, and inputs the next parallel data into the shift) register; A parallel-to-serial conversion method characterized by the ability to change p@.