SU922728A1 - Device for shaping carry signal at adding multiphase codes - Google Patents

Description

(54) DEVICE FOR SIGNAL FORMATION

TRANSFER AT SUMMIAVATION MULTIPHASE

CODES2

The invention relates to digital technology and is intended primarily for use in DC and AC electric drives with digital control, as well as automation systems.

Digital electric drives are known, where the addition of digital signals in the higher order of a multi-phase code is used, taking into account the result of the addition (transfer signal) in the lower order bits and.

A known adder for operation with multiphase codes (base pu2) where a matrix adder with the sizes of php and a transfer adder size of 2xp are used. From this adder can be selected circuit. forming a transfer signal to the higher bit, which contains the matrix of the | transfer | word and a part of the square matrix elements below the main diagonal 2.

A distinctive feature of such a device is high speed, but it contains many elements and requires multiple conversions from code to code.

Closest to the invention is a device for generating a transfer signal that can be extracted from the adder, with one operand coming directly in a multi-phase code, and the second is converted into an intermediate code in a decoder unit. The input buses of the first operand arrive at the input of the transfer addition block of 2xp / 2, whose output buses, together with

10 output busses of the decryption unit are fed to the matrix adder with the sizes n / 2xp / 2, some of the elements of this matrix adder participate in the formation of the transfer signal

15 in high bit, weekend chinz. These elements of the matrix adder are connected to the outputs of the logic unit, the other input lines of which are connected to the operand buses of bit 20 and the transfer bus from the least significant bit 3.

This device contains fewer elements, but also requires multiple conversions from code to code, and, moreover, the number of equipments is still relatively

is great.

The purpose of the invention is to increase speed and reduce the number of

30 equipment. The goal is achieved by the fact that in a device for forming a transfer signal when summing multiphase codes containing AND and OR elements in each bit, as well as decryption nodes of the highest bit combinations of the first and second operands of the device, whose inputs are connected to buses inverse values. The scientific research institutes of odd numbers and direct value busses of even bits of a given bit representation of the multi-phase code of the first and second operands of the device, respectively, when summing numbers with calculating only the transfer values of the first inputs | of the elements And of the first group are connected to the corresponding outputs of the high-order decoding nodes combinations of the first operand, the second input of the odd element and the first group is connected to the bus of the inverse value of the corresponding even binary bit representation of this bit Yes, the multi-phase code of the second operand to the device, the second input of each even element of the first group is connected to the direct value bus of the subsequent binary binary representation of the bit of the multi-phase code of the second operand of the device, the first inputs of the elements of the second group are connected to the corresponding outputs decryption node of the highest bit combinations of the second operand, the second input of each odd element And the second group is connected to the bus inverse value of the corresponding odd binary bit Yes views of this bit of multi-phase code of the first operand of the device, the second input of each even element of the second group connects the bus with the direct value of the subsequent odd binary bit representation of the bit of a multi-file code of the first operand of the device, output of the elements of the first and second groups and the first and second elements And are connected to the inputs of the first element OR, the output of which is connected to the output of the transfer from a given bit of the device, the first inputs of elements AND of the third and fourth groups of with the outputs of the decryption nodes of the higher-order bit combinations of the first and second operands, respectively, starting from the second outputs, the second input of each odd element AND of the third group is connected to the inverse bus of the corresponding even binary bit representation of this bit of the multi-phase code of the second operand device , the second input of each even-numbered element of the third group is connected to the busbar value of the subsequent odd binary bit representation of this bit of the multi-phase code of the second o device peranda with the exception of the last binary bit, the second input of each odd element and the fourth group is connected to the inverse bus value of the corresponding even binary bit representation of the bit of the multiphase code of the first operand device, the second input of each even element of the fourth group is connected to the direct bus the value of the subsequent odd binary bit representation of the given bit of the multi-phase code of the first operand of the device with the exception of the last binary bit Yes, the inputs of the first element I are connected to the buses of the inverse values of the first binary bits of the representation of the given multi-phase code of the first and second operands of the device, the outputs of the elements AND of the third and fourth groups, the outputs of the third. and the fourth And elements and the first outputs of the decryption nodes of the higher-order bit combinations of the first and second operands are connected to the inputs of the second OR element, the output of which is connected to the first input of the second element And, the second input of which is connected to the VH.ODOM of the transfer to this bit of the device, the inputs the third element I is connected to the bus of the inverse value of the first binary bit of the representation of the given bit of the multiphase code of the first operand of the device and with the bus of the direct value of the last binary bit of the representation given the multi-phase code of the second operand of the device, the inputs of the fourth element And are connected by the bus and the inverse value of the first binary bit of the multi-phase code of the second operand of the device and the direct value bus of the last binary bit of the multi-phase bit: code of the first operand devices. Fig. 1 shows a functional diagram of a single bit of the device; Fig. 2 shows the relationship between the signals of the five-phase code and the signals of the ordinary decimal code; in FIG. 3, the addition table. The device contains nodes 1 and 2 of decryption of the higher-order bit combinations of the first and second operands, containing the elements AND 3 - b-. , and elements And 7 - 10 respectively, elements And 11 and 12, elements And 13 - 16, forming the first group, elements And 17, - 20, forming the second group, elements OR 21 and 22, elements And 23 - 25, forming the third group, the element And 26, the elements And 27 i. 29 which form the fourth group, element I 30, tires 31 and 32 direct and inverse values of bits of representation of the given bit of the first and second operands A and B.

The first inputs of the elements 3–6 are connected to the bus 31 of the signal A ,, and the second inputs are connected to the buses 31 of the signals Au / A, AZ and A fj, respectively. The first inputs of the elements 7 to 10 are connected to the bus 32 of signal B, and the second inputs to the buses 32 of the signals By, B of B and B 0. The buses of 31 and 32 of the signals A ,,,, Bxf are connected to the inputs of the element I C

The outputs of elements 3–10 are connected to the first input of elements I 13 20, respectively, the second inputs of which are connected to buses 32 signals WD, B (J, B and Bt; and buses 31 signals A, A, A, A and A, respectively.

The outputs of the elements And 4, 5, b, 8, 9 and 10 are connected to the first inputs of the elements And 23, 24, 25, 27 and 28, respectively, the second inputs of which are connected to the buses 32 of the signals Bi, Bj, B, A (He, respectively The inputs of the element And 26 are connected to the buses 31 and 32 of the signals A and W. The inputs of the element 30 are connected to the bus 31 and 32 of the signals AS, BS- The inputs of the element OR 21 are connected to the outputs of the elements 11 11, its output 33 This bit of the device. The inputs of the element OR 22 are connected to the outputs of the elements AND 3, -7, 23 - 30, and the output - to the input of the element AND 12, another input of which is connected to the input 34 transfers from the previous bit of the device.

For consideration of device operation, we turn to the relationship between a multi-phase code and a conventional digital code.

Figure 2 shows the signals of the four-phase code (Q, QQ, Q, Qj) and the corresponding signals of the usual digital code, which are expressed by the dependencies O

 2 9з04 ,, ,,, Qi, .Q3, 7.,, Q5Q ,.

According to these dependencies, the AND 3 - 6 elements give a signal that the code combination at their input corresponds to the following digits of the usual digital code of the first AT 9 operand,

And, - 4 8- - 9,

A. A ,,,: 7 9,

A.- 6 V 7 V 8 V 9

m: Accordingly, the elements 7 - 10 give a signal about ngshichiiin their input code combination. corresponding to the following digits of the normal digital code of the second operand

B -Bfi6v7 8v9,

BV Vl,, §4 8 W -9,

 9.

In accordance with the table of addition of digital signals A and B (Fig. 3), the transfer to the senior bit of the RC should be formed with the numbers of the result of the addition below the main diagonal, and if there is a transfer from the younger category of the PK-l, also with the numbers of the main diagonal

0 diagonal 9.

The many digits of the result of the addition, which determine the transfer signal P ,; can be written by a logical formula

,

where M is the set of digits of the result of addition below the main diagonal; M. Г1 - a set of digits of the result of the addition, including the main diagonal and below. The signal of a set of M is formed by, respectively, at the outputs of the elements which, through the OR element 21, arrive at the output 33. The signal of the set M is formed, respectively, at the outputs of the elements OF, 7, 23-30, which through the element OR 22 are fed to the first input of the element And 12, .to the second input — of which the transfer signal P is supplied, from input 34.

0

Obtaining the transfer signal. Directly from the signals of the phases of the operands, the performance of the proposed device was improved and the equipment was reduced by eliminating intermediate operations for calculating the specific value of the result of the addition required to obtain the transfer signal in the full adder.

The symmetry of the multi-phase code

0 and the simplicity of its decoding allowed to get the transfer signal from the subsets that overlap each other many times, which increased the reliability of the device as a whole.

five

Claims (3)

1. USSR author's certificate in application number 2352761 / 18-24, cl. G 06 F 7/385, 1978. 0 2, Prangishvili IV and others. Microelectronics and homogeneous structures for the construction of logical computing devices. M, Science, 1967, p. 176, fig. 4.22. 3. USSR author's certificate for application no. 2585230 / 18-24, class G 06 F 7/385, 1978 (prototype).  I iff .-F iff lE 27: Ey .