JPS5851577A - Semiconductor device - Google Patents

Abstract

PURPOSE:To enhance the impact resistance voltage characteristics of a semiconductor device by connecting a P-N junction parallel to a Schottky junction. CONSTITUTION:A GaAs MESFET11 having a drain electrode 16, a source electrode 17 and a gate electrode 18 is formed by an N type GaAs active layer 13 on a semi-insulating GaAs substrate 12 and forming the Schottky gate electrode 18 on the layer 13. An N type region 14 forming P-N junction 20 is formed by injecting an impurity to the layer 13, and the region 14 contains higher N type impurity than the layer 13 of the FET11. When a P type region 15 is formed on the region 14, the reverse breakdown voltage BVPN of the P-N junction becomes smaller than the reverse breakdown voltage BVSC of Schottky junction. In order to provide BVPN<BVSC, the thickness of the region 14 can be increased than that of the layer 13. In this manner, the P-N junction is broken down before the Schottky junction breaks down, thereby absorbing the impact voltage energy.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device having a Schottky junction, and proposes a structure that improves the impact voltage resistance of the Schottky junction.

When a shock voltage is applied from the outside to a semiconductor device having a Schottky junction for some reason, and as a result, a large current flows through the Schottky junction due to breakdown of the Schottky junction, etc. It is susceptible to degeneration and can easily lead to permanent destruction. Therefore, when using a semiconductor device with a Schottkill junction, it has been necessary to be extremely careful in handling it, and there have been disadvantages such as the need for a separate circuit to protect the semiconductor device from shock voltage. Ta.

37.1 The present invention is one in which a pn junction connected in parallel to a Schottky junction or an element including a pn junction is formed on the same substrate, and one shock voltage is absorbed by the pn junction.
The present invention provides an integrated semiconductor device with significantly improved impact voltage resistance.

The present invention will be described in detail below using an example in which the present invention is applied to a GaAs ME S jET (GaAs Schottky gate field effect transistor).

GaAsMESFET is usually a semi-insulating G
aA,! An n-type layer formed on one substrate is used as an active layer. In this structure, if the pn junction that protects the Schottky junction from impact voltage is formed by forming an oppositely conductive shadow region in the same active layer as the Schottky junction, then
The reverse breakdown voltage BVpn of the pn junction is greater than or approximately the same value as the reverse breakdown voltage BVsc of the Schottky junction. Even in this case, the shock voltage resistance of the Schottky junction is improved, but the shock voltage resistance can be further improved by making BVpn smaller than BVsc. This means that before the Schottky junction yields, pn
It is thought that the joining is due to rain.

FIG. 1 (8) shows GaAsM E S F E T 1
1 and a diode that protects the Schottky junction from impact voltage, that is, a pn junction 2o, are formed on the same substrate,
Moreover, it shows a structure in which BVpn<BVgc. Further, FIG. 1(B) is an equivalent circuit diagram showing the connection state of FIG. 1(3). Drain electrode 16. Source electrode 1
7. GaAs MESFETl consisting of gate electrode 18
1 has a thickness of 0.1 to 0.4 μm formed by epitaxial growth on a semi-insulating GaAs substrate 12;
Impurity concentration "FET is o, 6~3X1017crn-3
An n-type aAs active layer 13 is used, and a Schmittkey gate electrode 18 is formed on this layer 13.

On the other hand, the thickness of forming the pn junction 2o is 0.2 to 1.0 μm.
The n-shaded region 14 is formed by ion-implanting impurities such as Si, SjL, or S into the layer 13, and the n-shade region 14 has an n-type impurity concentration npn lower than that of the n-type active layer 13 of GaAsM E S F E T. 3~1oX1017ffl-
It is set as high as 3. Create a p shadow area 15 in this 5
, - if BVpn<BVsc and null.

Note that in order to obtain BVpn (BVsc), as shown in the above embodiment, the impurity concentration in the n-shaded region 14 of the p-n junction should be greater than the impurity concentration in the n-type active region 13 of the GaAs MESFET. Or, the thickness dpn of the n shadow region 14 of the pn junction is GaAs+M E
S F E T t7) Thickness of n-type active layer 13
If the impurity concentration of the p-shaded region 15 in FIG. can do. Such a high impurity concentration p shadow region 16 is formed by, for example, Zn diffusion or Zn in a closed tube.

If ion implantation of p-type impurities such as Be and Mg is used,
Can be easily formed.

By applying the present invention, the high frequency characteristics of GaAs FETs for high frequencies of 100 MHz or higher can be significantly reduced.
/-Ikushita 1. In order to prevent this, it is desirable to design the capacitance of the pn junction to be 2 pF or less and the series resistance at the time of breakdown to be IQOΩ or less. In addition, the smaller the reverse breakdown voltage BVpn of the pn junction, the better the impact voltage resistance, but on the other hand, the lower limit of BVpn is determined by the gate-source breakdown voltage required for the FET, and BVpn is usually It is conveniently set to 3-15v.

In the above manner, as shown in Figure 1, GaAsM for high frequency
By integrally forming the E S F E T 11 and the pn junction 2o, the shock voltage resistance, which is originally about 1 erg, can be increased to over 80 erg, and high voltage resistance can be achieved without the need for any separate circuit components. A high-performance Schottky junction semiconductor device can be created.

FIGS. 2(8) to (E) show the present invention in dual-gate GaA
It is a connection diagram of an example applied to sMESFET11'.

18a and 18b are the first. 2nd gate, 20a
.

20b is a pn junction for protection, FIG. 2 (8), ρ.

77) uses pn junctions connected in series in opposite directions, and exhibits a protective effect against both positive and negative impact voltages.

The above embodiments are cases in which the present invention is applied to GaAs MESFETs, but the present invention is also effective when using other semiconductor materials such as St and Inl'.
This is effective not only for ET but also for semiconductor devices in general having Schottky junctions. FIG.
21 shows an example where o is connected, and 21 indicates the metal electrode side.

As described above, according to Akira Honjo, it is possible to provide a Schottky junction semiconductor device with excellent shock resistance characteristics without adding any separate circuit components, and this contributes to the realization of high-performance semiconductor devices. This will make a major contribution.

[Brief explanation of drawings]

FIG. 1 (5) is a schematic cross-sectional view of a GaAs MESFET and a pn junction of an embodiment of the present invention formed on the same substrate, and FIG. Circuit diagrams showing the state of connection, Fig. 2 (5) to (E) are circuit diagrams of an embodiment in which the present invention is applied to a Puar gate MESFET, and Fig. 3 (8) to (E) are circuit diagrams in which the present invention is applied. 7 Yonotoki one junction and p
It is a figure which shows the connection example of n junction. 11, 11'=-GaAgMESFET,
12--=semi-insulating GaAs substrate, 13...-
n-type active layer formed by epitaxial growth, 14
...-n shadow region formed by ion implantation of Si,
15...p shadow area, 18, 18a, 18b-'
-, )y' - %, 20-- pn junction. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure (A) 17 Figure 2 (A) Figure 2 (C) Figure 2 (E)

Claims (1)

[Claims] (1) A semiconductor device characterized in that a pn junction connected in parallel with a Schottky junction or an element including a pn junction are formed on the same substrate. (2> The semiconductor device according to claim 1, wherein the reverse breakdown voltage of the pn junction is smaller than the reverse breakdown voltage of the Schottky junction. @) The Schottky junction is Ga As 2. The semiconductor device according to claim 1, wherein the semiconductor device constitutes a gate of a field effect transistor. ←) A short key junction constitutes the gate of a GaAs field effect transistor, a pn junction semiconductor region of one conductivity type is formed in a part of the active layer of one conductivity type of this transistor, and the impurity concentration of the semiconductor region is 2. The semiconductor device according to claim 1, wherein the impurity concentration is higher than that of the active layer. β) A Schottky junction constitutes the gate of a GaAs field effect transistor, and a pn junction semiconductor region of one conductivity type is formed in a part of the active layer of this transistor, and the thickness of the semiconductor region is equal to that of the semiconductor. The semiconductor device according to claim 1, wherein the semiconductor device is thicker than the thickness of the layer.