JPS5850851A - Parallel-to-series converting circuit of telemeter transmitter - Google Patents

Abstract

PURPOSE:To reduce the size and power consumption of a device by controlling the timing of data by a word signal for input parallel data before parallel/series conversion, and thus decreasing the number of registers for conversion to one, without reference to the number of input data. CONSTITUTION:Before input parallel data D1,000-D111,...Dn00-Dn11 are set in a parallel/series conversion register R1, said data are timed in inputting to the register R1 by corresponding words W1-Wn. Under this timing control, said data are set by a trigger T1 in word series to the register R1. After the setting, serial transmitted data SD are outputted from the output Q of the parallel/ series conversion register by a clock signal C for the parallel/series conversion register, and thus the processing is performed by one register R1 to reduce the size and power consumption of the device.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a signal parallel-to-serial conversion circuit (hereinafter referred to as parallel-to-serial conversion circuit) in a telemeter system transmitter.

By inverting the transmitted signal and sending it again, the receiving side compares both signals and checks the transmission line system. Conventionally, parallel/direct conversion of data has been done manually.
It had a register for direct conversion. This will be explained with reference to FIG. RI-Rn is a parallel/direct conversion register). Parallel data DIO [1 to D1.1 is set in the R register by the trigger of T, and is output from Ql as serial data by the clock C, and is conditioned by the word signal W1 by the AND gate A1, and at the timing of this word signal W1. It becomes transmission data and is sent to the receiving side. Q. Inversion of the output is performed by inverter 1. Parallel/direct conversion for parallel data Dnoo to Dno is similarly performed by parallel/direct conversion register Rn. Therefore, when transmitting a plurality of parallel data, a plurality of parallel/serial conversion registers are required, resulting in a large circuit configuration.

The present invention solves this drawback by sorting the parallel manually input data using word signals corresponding to the data before manually inputting a plurality of parallel input data to the register for parallel/direct conversion. This is intended to simplify the circuit configuration by using only one register.

When performing reversal transportation data transmission, the data that has been parallel/directly converted at the time of initial transmission must be inverted and sent again, and registers are not possible, but the number of register configurations for parallel/direct conversion and reversal transportation is required. The system is constructed using a Lujistor configuration to accommodate human-powered parallel data.

An embodiment of the invention is shown in FIG. In the same figure.

SD is serial transmission data, and the same reference numerals as in FIG. 1 indicate the same items. Human parallel data DH(y)-1)Hl, DnO
o""' Dnl 1 is a word signal W corresponding to each manual data before being set in the parallel/direct conversion register R,
-Wn provides manual timing for the parallel/direct conversion register R.

As a result, multiple parallel data can be transferred to parallel/direct conversion register R3.
Trigger T is set word serially. After setting, clock C causes Q, and serially sends data S.
D and is sent out. On the other hand, the inverter 11 sends the inverted data again from the clock CK to the clock Q. Note that R is a reset signal for the register R1. ++
, □ That is, the word signal W corresponding to each manual parallel data,
~The timing control of data by Wn, which was performed after the parallel/direct conversion of the data, is performed manually before conversion, thereby reducing the number of registers for parallel/direct conversion from multiple parallel/direct conversion registers to one. be.

As described above, according to the present invention, the number of parallel/direct conversion registers can be reduced to one regardless of the number of input data to the telemeter transmitter, thereby reducing the number of constituent boards, downsizing the device, and reducing power consumption. .

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional parallel/serial conversion circuit in a telemeter transmission device, and FIG. 2 is a block diagram showing a parallel/serial conversion circuit of a telemeter transmission device according to the present invention. D100~Dm + Dnoo ""-Dnu is a manual parallel text, R. ~Rn is parallel/direct conversion register, T, -Tn is parallel/direct conversion register manual trigger signal + 'I~In is inverter for inverting continuous transmission, W1~Wn is word conversion register, C is for parallel/direct conversion register A clock signal, R is a reset signal, QI is the output of the parallel/direct conversion register, and SD is serial transmission data.

Claims (1)

[Claims] In a telemeter transmitter, multiple sets of parallel data corresponding to each word signal are manually input to a parallel-to-serial conversion circuit at the timing of the word signal, and the parallel-to-serial conversion circuit converts the data converted into serial data to the timing of a clock signal. At the same time, the parallel data is sent to the receiving side via the inverter, and the serial data of the parallel-to-serial conversion circuit is input again, and then sent to the receiving side at 4pm of the next clock signal.
Series conversion circuit.