JPS5848921A - Preparation of semiconductor device - Google Patents

Preparation of semiconductor device

Info

Publication number
JPS5848921A
JPS5848921A JP56147203A JP14720381A JPS5848921A JP S5848921 A JPS5848921 A JP S5848921A JP 56147203 A JP56147203 A JP 56147203A JP 14720381 A JP14720381 A JP 14720381A JP S5848921 A JPS5848921 A JP S5848921A
Authority
JP
Japan
Prior art keywords
substrate
semiconductor device
reinforcing material
glass
increase
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56147203A
Other languages
Japanese (ja)
Inventor
Kiichi Usuki
臼木 喜一
Shunichi Kai
開 俊一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP56147203A priority Critical patent/JPS5848921A/en
Publication of JPS5848921A publication Critical patent/JPS5848921A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE:To prevent crack of Si substrate, drop of breakdown voltage and increase of leakage current by forming identically the protection film for the bevel surface using the multi-element system glass material for bonding the Si for substrate protection and the substrate. CONSTITUTION:The side of Si substrate 21 having the PN junction is subjected to the beveling, the SiO2 films 22, 23 are deposited and the film 23 is provided with an aperture. Then, the multi-element glass materials 24, 25 are deposited by the cataphoresis method. The Si reinforcing material 26 which is larger in diameter than the substrate 21 is baked in the O2 ambient at a temperature of about 800 deg.C with the glass 25 and then bonded. According to this method, crack of substrate, drop of breakdown voltage, increase of leakage current can be avoided.

Description

【発明の詳細な説明】 この発明は基板保護用補助材例えば8iと基板との接着
材に多成分系ガラスを用いてベベル面との保護膜を同一
に形成するようにした半導体装置の製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention is a method for manufacturing a semiconductor device in which a multi-component glass is used as an adhesive between an auxiliary material for protecting a substrate, such as 8i, and a substrate, and a protective film is formed on the beveled surface in the same manner. Regarding.

まず、第1図に従来の代表的な半導体装置の断面を示す
。図において、11はPN接合を有する半導体基板であ
る。そして、この半導体基板11に機械的強度を増すた
めにPH1側に接着材12を用いて基板11と補強材1
3とを接着している。一般的に接着材12としてはAI
が多く用いられ、補強材13としてはタングステンやモ
リff”ンが用いられる。ところで、この補強材13は
P層の電極も兼ねている。そして、基板11と補強材I
Jが接着された後基板11の側面に5and Blas
t法等でベベル面が形成され、表面処理を行った後En
cap剤等で表面保護膜15が形成される。最近では高
耐圧化、高信頼性化、大容量化の要求に沿って大口径化
されている。しかし、従来の方法では基板11と補強材
13との熱膨張係数の差に依シ熱応力が基板11内部に
生じる。この熱応力は基板11のクラック、耐圧の低下
、リーク電流の増大等の原因となる。また、補強材13
として用いられるタングステン、モリブデンはコストも
高く、ペレットのコストの1/2〜1/3を占めている
First, FIG. 1 shows a cross section of a typical conventional semiconductor device. In the figure, 11 is a semiconductor substrate having a PN junction. Then, in order to increase the mechanical strength of this semiconductor substrate 11, an adhesive 12 is used on the PH1 side to bond the substrate 11 and the reinforcing material 1.
3 are glued together. Generally, the adhesive material 12 is AI.
is often used, and tungsten or molybdenum is used as the reinforcing material 13. By the way, this reinforcing material 13 also serves as an electrode for the P layer.
5and Blas on the side of the board 11 after J is glued.
A beveled surface is formed using the t method, etc., and after surface treatment, En
A surface protective film 15 is formed using a cap agent or the like. Recently, the diameter has been increased to meet the demands for higher voltage resistance, higher reliability, and larger capacity. However, in the conventional method, thermal stress is generated inside the substrate 11 due to the difference in thermal expansion coefficient between the substrate 11 and the reinforcing material 13. This thermal stress causes cracks in the substrate 11, a decrease in breakdown voltage, an increase in leakage current, and the like. In addition, the reinforcing material 13
The cost of tungsten and molybdenum used as pellets is high, accounting for 1/2 to 1/3 of the cost of pellets.

この発明は上記の点に鑑みてなされたものでその目的は
基板保護用補強材と基板との接着材に多成分系ガラスを
用いてベベル面との保護膜を同一に形成するようにして
基板のクラック、耐圧の低下、リーク電流の増大を防止
することができる半導体装置の製造方法を提供すること
にある。
This invention has been made in view of the above points, and its purpose is to form a protective film on the beveled surface of the substrate by using multi-component glass as an adhesive between the reinforcing material for protecting the substrate and the substrate. An object of the present invention is to provide a method for manufacturing a semiconductor device that can prevent cracks, a decrease in breakdown voltage, and an increase in leakage current.

以下、図面を参照してこの発明の一実施例を説明する。Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

第2図囚ないしくQはこの発明に係る半導体装置の製造
方法の各工程における断面図を示している。第2図に)
においてPN接合を有する半導体基板21の側面はベベ
ル加工されている。また、22は酸化膜で、P層側の酸
化膜23は選択的に酸化膜が除去されている。次に、第
2図(B)K示すように電気泳動法によシ多成分系ガラ
ス24及び25を附着させる。ここで、半導体基板21
の側面は附着された多成分系が2ス24は表面保!i!
膜として、半導体基板2ノのP層側の多成分系がラス2
5は接着剤として用いられる。次に、第2図C)に示す
ように補強材26としてSlが用いられておシ、この補
強材26は後の工程で電極数シの為にドーナツ状に補強
材23内部に穴孔があけられてお)、その補強材23の
直径は81基板21の直径よシも大きい。この補助材2
3と81基板21はベベル面の多成分系ガラスの焼成工
程に於てP層側にもガラス膜が有るので同時に接着され
る。
FIGS. 2 to 2 Q show cross-sectional views at each step of the method for manufacturing a semiconductor device according to the present invention. (See Figure 2)
The side surface of the semiconductor substrate 21 having the PN junction is beveled. Further, 22 is an oxide film, and the oxide film 23 on the P layer side is selectively removed. Next, as shown in FIG. 2(B)K, multi-component glasses 24 and 25 are deposited by electrophoresis. Here, the semiconductor substrate 21
The multi-component system attached to the side surface of 24 is the surface protection! i!
As a film, the multi-component system on the P layer side of the semiconductor substrate 2 is the last layer 2.
5 is used as an adhesive. Next, as shown in FIG. 2C), Sl is used as the reinforcing material 26, and this reinforcing material 26 has a donut-shaped hole inside the reinforcing material 23 in order to accommodate the number of electrodes in a later process. The diameter of the reinforcing member 23 is also larger than the diameter of the 81 substrate 21. This auxiliary material 2
3 and 81 substrates 21 are bonded together at the same time since there is a glass film on the P layer side during the firing process of the multi-component glass on the beveled surface.

ここで、焼成温度は600°〜800℃で雰囲気は02
である。この様にして作られた素子はその後電極付は組
み立てられる。
Here, the firing temperature is 600° to 800°C and the atmosphere is 0.2°C.
It is. The device made in this way is then assembled with electrodes.

しかして、接着剤としてA1を用いた場合第3図に示す
場合が考えられる。第3図■は基板徹 31と補蜘材32を先に接着させて、その後多成分系ガ
ラスを形成してその後補強材31を接着する方法である
。そして、第3図い)の場合は多成分系ガラスの焼成温
度の方がAI OA11oy温度よシも高い為ガラス焼
成時に基板31と補廊 餅材32が剥離する。
Therefore, when A1 is used as the adhesive, the case shown in FIG. 3 can be considered. FIG. 3 (3) shows a method in which the substrate plate 31 and the reinforcing material 32 are first bonded together, then a multi-component glass is formed, and then the reinforcing material 31 is bonded. In the case of Figure 3), the firing temperature of the multi-component glass is higher than the AI OA11oy temperature, so the substrate 31 and the mochi material 32 separate during glass firing.

また、第3図CB)の場合AIの飛び散)による耐圧劣
化、基板取扱上の機械的衝撃によるGlasmクラック
の発生等の問題が発生する。
Further, in the case of FIG. 3 CB), problems such as breakdown voltage deterioration due to AI scattering and generation of Glasm cracks due to mechanical impact during handling of the substrate occur.

以上詳述したようにこの発明によれは、基板保護用のS
tと基板との接着材に多成分系がラスを用いてベベル面
との保護膜を同一に形成するようにしたので、81基板
のクラック、耐圧の低下、リーク電流の増大を防止する
ことができる。
As described in detail above, according to the present invention, the S
A multi-component lath is used as the adhesive between the T and the substrate to form the same protective film on the beveled surface, preventing cracks in the 81 substrate, a decrease in withstand voltage, and an increase in leakage current. can.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の半導体装置の断面図、第2図(4)ない
しくQはそれぞれこの発明の一実施例に係る半導体装置
の製造方法の各工程の断面図、第3図(4)及び0)は
それぞれこの発明の他の実施例を示す半導体装置の断面
図である。 11.21・・・半導体基板、12−・・接着材、颯
FIG. 1 is a cross-sectional view of a conventional semiconductor device, FIGS. 2 (4) to Q are cross-sectional views of each step of a method for manufacturing a semiconductor device according to an embodiment of the present invention, and FIGS. 3 (4) and 0) are cross-sectional views of semiconductor devices showing other embodiments of the present invention. 11.21... Semiconductor substrate, 12-... Adhesive material, Stainless steel

Claims (1)

【特許請求の範囲】[Claims] (1)基板保護用のStと基板との接着材に多成分系が
ラスを用い、ベベル面との保護膜を同一に形成すること
を特徴とする半導体装置の製造方法。 f211ミクロン以上の膜厚の酸化膜をベレットと補助
材との間に設定したことを特徴とする特許請求の範囲第
1項記載の半導体装置の製造方法。
(1) A method for manufacturing a semiconductor device, characterized in that a multi-component lath is used as an adhesive between St and the substrate for protecting the substrate, and a protective film is formed on the beveled surface in the same manner. 2. The method of manufacturing a semiconductor device according to claim 1, wherein an oxide film having a thickness of f211 microns or more is provided between the pellet and the auxiliary material.
JP56147203A 1981-09-18 1981-09-18 Preparation of semiconductor device Pending JPS5848921A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56147203A JPS5848921A (en) 1981-09-18 1981-09-18 Preparation of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56147203A JPS5848921A (en) 1981-09-18 1981-09-18 Preparation of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5848921A true JPS5848921A (en) 1983-03-23

Family

ID=15424886

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56147203A Pending JPS5848921A (en) 1981-09-18 1981-09-18 Preparation of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5848921A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1992005590A1 (en) * 1990-09-14 1992-04-02 Advanced Photonix, Inc. Light responsive avalanche diode

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1992005590A1 (en) * 1990-09-14 1992-04-02 Advanced Photonix, Inc. Light responsive avalanche diode

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