JP3114459B2 - Method for manufacturing piezoelectric element - Google Patents

Method for manufacturing piezoelectric element

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Publication number
JP3114459B2
JP3114459B2 JP26164793A JP26164793A JP3114459B2 JP 3114459 B2 JP3114459 B2 JP 3114459B2 JP 26164793 A JP26164793 A JP 26164793A JP 26164793 A JP26164793 A JP 26164793A JP 3114459 B2 JP3114459 B2 JP 3114459B2
Authority
JP
Japan
Prior art keywords
voltage
substrate
glass layer
piezoelectric
bonding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP26164793A
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Japanese (ja)
Other versions
JPH0794801A (en
Inventor
克彦 田中
洋一 持田
英一 高田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Murata Manufacturing Co Ltd
Original Assignee
Murata Manufacturing Co Ltd
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Priority to JP26164793A priority Critical patent/JP3114459B2/en
Publication of JPH0794801A publication Critical patent/JPH0794801A/en
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Publication of JP3114459B2 publication Critical patent/JP3114459B2/en
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Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、圧電セラミックスと基
板とを接合一体化する圧電素子の製造方法に関するもの
である。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a piezoelectric element for joining and integrating a piezoelectric ceramic and a substrate.

【0002】[0002]

【従来の技術】図5には陽極接合を利用した圧電セラミ
ックス1とシリコン等の基板2とを接合一体化する方法
が示されている。陽極接合は一般的には図4に示すよう
に、ガラス板4とシリコンの基板2とを接合するもの
で、基板2とガラス板4を重ね合わせ、高温雰囲気中
で、電源6により基板2とガラス板4間に数100 Vの電
圧を印加することにより、ガラス層の可動イオンが移動
して、ガラス層とシリコン基板の間の静電引力により両
材料が密着し、さらに、ガラス層中の酸素とシリコン基
板のSiが結合することにより、基板2とガラス板4と
が接合一体化されるものである。
2. Description of the Related Art FIG. 5 shows a method of bonding and integrating a piezoelectric ceramics 1 and a substrate 2 made of silicon or the like using anodic bonding. The anodic bonding generally joins the glass plate 4 and the silicon substrate 2 as shown in FIG. 4. The substrate 2 and the glass plate 4 are overlapped, and the substrate 2 is When a voltage of several hundred volts is applied between the glass plates 4, mobile ions of the glass layer move, and the two materials adhere to each other due to electrostatic attraction between the glass layer and the silicon substrate. By bonding oxygen and Si of the silicon substrate, the substrate 2 and the glass plate 4 are joined and integrated.

【0003】上記陽極接合を利用して圧電セラミックス
1とシリコンの基板2を接合するには、図5に示すよう
に、圧電セラミックス1の接合面に無機接着層としてガ
ラス層4を形成し、このガラス層4を介して基板2と圧
電セラミックス1と重ね合わせ、300 ℃〜600 ℃の高温
炉中で、電源6により基板2とガラス層4間に数100V
の電圧を印加することにより、基板2とガラス層4との
陽極接合が行なわれ、これにより、圧電セラミックス1
と基板2とを一体化した圧電素子が作製される。
In order to join the piezoelectric ceramics 1 and the silicon substrate 2 using the above-described anodic bonding, as shown in FIG. 5, a glass layer 4 is formed as an inorganic adhesive layer on the joining surface of the piezoelectric ceramics 1, and The substrate 2 and the piezoelectric ceramics 1 are superimposed on each other via the glass layer 4, and several hundred volts are applied between the substrate 2 and the glass layer 4 by a power source 6 in a high-temperature furnace at 300 to 600 ° C.
Anodic bonding between the substrate 2 and the glass layer 4 is performed by applying
And a substrate 2 are integrated to produce a piezoelectric element.

【0004】[0004]

【発明が解決しようとする課題】陽極接合により圧電セ
ラミックス1と基板2とを接合する方式は、接合温度が
例えば400 ℃あるいは500 ℃と高く、このため、陽極接
合後、温度を常温に冷却していく過程で、圧電素子に大
きな内部歪が残留し、この残留歪が圧電素子の機械的強
度を低下させたり、素子の特性を低下させるという問題
があった。
In the method of joining the piezoelectric ceramics 1 and the substrate 2 by anodic joining, the joining temperature is as high as 400 ° C. or 500 ° C., and therefore, after the anodic joining, the temperature is cooled to room temperature. During the process, a large internal strain remains in the piezoelectric element, and there is a problem that the residual strain lowers the mechanical strength of the piezoelectric element and degrades the characteristics of the element.

【0005】本発明は上記従来の課題を解決するために
なされたものであり、その目的は、高温の陽極接合によ
って生じる素子の残留応力をできる限り低減しようとす
る圧電素子の製造方法を提供することにある。
The present invention has been made to solve the above-mentioned conventional problems, and an object of the present invention is to provide a method of manufacturing a piezoelectric element in which residual stress of the element caused by high-temperature anodic bonding is reduced as much as possible. It is in.

【0006】[0006]

【課題を解決するための手段】本発明は上記目的を達成
するために、次のように構成されている。すなわち、本
発明は、圧電セラミックスと基板とを接着層を介して接
合一体化する圧電素子の製造方法において、前記圧電セ
ラミックスの接合面に無機接着層を形成し、この無機接
着層を介して基板と圧電セラミックスとを重ね合わせ、
接合温度雰囲気中で基板と圧電セラミックス間に電圧を
印加することによって圧電セラミックスと基板とを接合
一体化することを特徴として構成されている。
The present invention is configured as follows to achieve the above object. That is, the present invention provides a method for manufacturing a piezoelectric element in which a piezoelectric ceramic and a substrate are joined and integrated via an adhesive layer, wherein an inorganic adhesive layer is formed on a joint surface of the piezoelectric ceramic, and the substrate is interposed via the inorganic adhesive layer. And piezoelectric ceramics
The piezoelectric ceramics and the substrate are joined and integrated by applying a voltage between the substrate and the piezoelectric ceramics in a bonding temperature atmosphere.

【0007】[0007]

【作用】上記構成の本発明において、圧電セラミックス
と基板とを無機接着層を介して接合するに際し、基板と
圧電セラミックス間に電圧を印加するようにしたので、
無機接着層を薄肉化しても、無機接着層の絶縁破壊が生
じにくくなり、これに伴い、印加電圧を直接無機接着層
に印加する場合に比べ印加電圧を高くすることができる
ので、その分接合温度を低くすることができ、接合温度
が低くなる分だけ圧電素子の残留内部歪が小さくなる。
In the present invention having the above structure, when the piezoelectric ceramic is bonded to the substrate via the inorganic adhesive layer, a voltage is applied between the substrate and the piezoelectric ceramic.
Even if the thickness of the inorganic adhesive layer is reduced, dielectric breakdown of the inorganic adhesive layer is less likely to occur, and accordingly, the applied voltage can be increased as compared with a case where the applied voltage is directly applied to the inorganic adhesive layer. The temperature can be lowered, and the residual internal strain of the piezoelectric element decreases as much as the bonding temperature decreases.

【0008】[0008]

【実施例】以下、本発明の実施例を図面に基づいて説明
する。図1には本発明の一実施例が示されている。本実
施例も陽極接合により圧電セラミックス1と基板2を接
合するものであるが、図5に示す従来例と異なる特徴的
なことは、陽極接合に際し、印加する電圧を基板とガラ
ス層4との間に印加するのではなく、圧電セラミックス
1と基板2間に印加するようにしたことである。
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows an embodiment of the present invention. In this embodiment, too, the piezoelectric ceramics 1 and the substrate 2 are joined by anodic bonding. However, a characteristic different from the conventional example shown in FIG. 5 is that the voltage applied between the substrate and the glass layer 4 at the time of anodic bonding is different. That is, the voltage is applied between the piezoelectric ceramics 1 and the substrate 2 instead of being applied between them.

【0009】図1において、ジルコンチタン酸鉛Pb
(Zrx Ti1-x )O3 系の圧電セラミックス1の両面
には研磨が施され、接合面側にスパッタ処理等により厚
さ数μm(この実施例では2μm)のパイレックスガラ
ス等のガラス層4が無機接着層として形成されており、
反対側の面には金属電極5aが蒸着等により形成されて
いる。
In FIG. 1, lead zircon titanate Pb
Both surfaces of the (Zr x Ti 1-x ) O 3 -based piezoelectric ceramic 1 are polished, and a glass layer of Pyrex glass or the like having a thickness of several μm (2 μm in this embodiment) is formed on the bonding surface by sputtering or the like. 4 is formed as an inorganic adhesive layer,
On the opposite surface, a metal electrode 5a is formed by vapor deposition or the like.

【0010】一方、シリコンの基板2の電極形成面には
同様に蒸着等により金属電極5bが形成されている。圧
電セラミックス1と基板2とを陽極接合する際には、基
板2の接合面と圧電セラミックス1とをガラス層4を介
して重ね合わせ、例えば400℃の接合温度の雰囲気中
で、電源6により圧電セラミックス1と基板2間に500
Vの電圧を印加する。そうすると、ガラス層4と基板2
とが陽極接合して圧電セラミックス1と基板2とが一体
化接合され、圧電素子が作製される。
On the other hand, a metal electrode 5b is formed on the electrode forming surface of the silicon substrate 2 by vapor deposition or the like. When the piezoelectric ceramics 1 and the substrate 2 are anodic-bonded, the bonding surface of the substrate 2 and the piezoelectric ceramics 1 are overlapped via the glass layer 4 and, for example, in an atmosphere at a bonding temperature of 400 ° C., the piezoelectric 500 between ceramics 1 and substrate 2
A voltage of V is applied. Then, the glass layer 4 and the substrate 2
Are anodically bonded to each other, and the piezoelectric ceramics 1 and the substrate 2 are integrally bonded to each other to produce a piezoelectric element.

【0011】本実施例では、接合時の印加電圧を圧電セ
ラミックス1と基板2間に、つまり、圧電セラミックス
1を介してガラス層4と基板2間に印加するように構成
したことで、次に示す効果が得られる。まず第1の効果
として、印加電圧に対するガラス層4の耐圧が高くな
り、絶縁破壊に対する安全性が高められる。図5に示す
従来例のようにガラス層4に直接電圧を加える方式で
は、印加電圧を大きくするとガラス層が絶縁破壊を起こ
すという心配があり、ガラス層4が一旦絶縁破壊を起こ
すと、その絶縁破壊部分がショート状態となり、その絶
縁破壊部分を通って電流がガラス層4とシリコン基板2
との間で流れるため、陽極接合のための電圧が得られ
ず、陽極接合ができなくなるという問題が生じる。
In this embodiment, the voltage applied at the time of bonding is applied between the piezoelectric ceramics 1 and the substrate 2, that is, between the glass layer 4 and the substrate 2 via the piezoelectric ceramics 1. The following effects can be obtained. First, as a first effect, the withstand voltage of the glass layer 4 with respect to the applied voltage is increased, and the safety against dielectric breakdown is enhanced. In the method in which a voltage is directly applied to the glass layer 4 as in the conventional example shown in FIG. 5, there is a concern that an increase in the applied voltage may cause a dielectric breakdown of the glass layer. The broken portion is in a short-circuit state, and current flows through the insulating broken portion and the glass layer 4 and the silicon substrate 2
Therefore, there arises a problem that a voltage for anodic bonding cannot be obtained and anodic bonding cannot be performed.

【0012】これに対し、本実施例では、圧電セラミッ
クス1を介してガラス層4に電圧を印加しているため、
印加電圧はガラス層4の平板面の全面に加わるため耐圧
が高くなり、しかも、図2に示すように、ガラス層4の
一部にピンホール状の絶縁破壊部7が生じても、ガラス
層4に直列に圧電セラミックスが形成されているため、
絶縁破壊個所7に流れる電流が圧電セラミックスの絶縁
抵抗で阻止されるため、絶縁破壊された局部個所を除い
てガラス層4と基板2との間に陽極接合に必要な電圧が
確保され、支障なく陽極接合を達成することができる。
On the other hand, in this embodiment, since a voltage is applied to the glass layer 4 via the piezoelectric ceramics 1,
Since the applied voltage is applied to the entire flat surface of the glass layer 4, the withstand voltage is increased. Further, as shown in FIG. Because piezoelectric ceramics are formed in series with 4,
Since the current flowing through the dielectric breakdown location 7 is blocked by the insulation resistance of the piezoelectric ceramic, the voltage required for anodic bonding between the glass layer 4 and the substrate 2 is secured except for the local location where the dielectric breakdown has occurred, and there is no trouble. Anodic bonding can be achieved.

【0013】第2に、前記の如くガラス層4の耐圧が高
められることで、従来例に比べ高い電圧を印加すること
ができ、その分、接合温度を低くできるという効果が得
られる。本発明者はこの効果を実験により実証してい
る。この実験結果の一例が表1に示されており、例え
ば、印加電圧が300 Vと低いときには、接合温度を500
℃という高い温度にしたときに陽極接合が得られ、それ
よりも低い例えば400 ℃の接合温度では陽極接合ができ
ないという結果を得ている。これに対し、印加電圧を50
0 Vまで高めると、接合温度を400 ℃に低くしても、陽
極接合が可能になっている。
Second, by increasing the withstand voltage of the glass layer 4 as described above, it is possible to apply a higher voltage than in the conventional example, and it is possible to obtain the effect of reducing the bonding temperature. The present inventors have demonstrated this effect by experiments. An example of this experimental result is shown in Table 1. For example, when the applied voltage is as low as 300 V, the junction temperature is set at 500 V.
The anodic bonding is obtained when the temperature is as high as ℃, and the anodic bonding cannot be performed at a lower bonding temperature of, for example, 400 ℃. In contrast, the applied voltage is 50
When the voltage is increased to 0 V, anodic bonding can be performed even when the bonding temperature is reduced to 400 ° C.

【0014】[0014]

【表1】 [Table 1]

【0015】上記実験結果の検討により、印加電圧が高
いほど、また、接合温度が高いほど陽極接合の可能性が
高められることが分かった。その理由は、印加電圧が高
いほど、また、接合温度が高いほど、ガラス層の可動イ
オンが移動しやすくなり、ガラス層4とシリコンの基板
2との間の静電引力が増大して陽極接合の可能性が高ま
るものと思われる。
Examination of the above experimental results shows that the higher the applied voltage and the higher the bonding temperature, the higher the possibility of anodic bonding. The reason is that as the applied voltage is higher and the bonding temperature is higher, the mobile ions in the glass layer are more likely to move, and the electrostatic attraction between the glass layer 4 and the silicon substrate 2 increases, resulting in anodic bonding. It seems that the likelihood of this will increase.

【0016】換言すれば、印加電圧が高められれば、そ
の分、接合温度を低くすることが可能となり、接合温度
が低くなれば、その分、内部残留歪も小さくなり、これ
により、圧電素子の内部歪による機械的強度が強くな
り、さらに、内部歪による素子特性の低下を防止できる
という効果が得られるのである。
In other words, the higher the applied voltage, the lower the bonding temperature can be, and the lower the bonding temperature, the lower the internal residual strain. This has the effect of increasing the mechanical strength due to the internal strain and preventing the deterioration of the device characteristics due to the internal strain.

【0017】上記した如く、本実施例では陽極接合時に
加える電圧をガラス層4に直接印加することなく、圧電
セラミックス1を介してガラス層4に印加しているが、
このように圧電セラミックス1を介して間接的にガラス
層4に電圧を印加しても、圧電セラミックス1はガラス
層4に比較して誘電率が大きいため、陽極接合に必要な
十分高い電圧をガラス層4に印加することができる。こ
のことは次のように説明できる。本実施例の陽極接合部
における等価回路は図3のように表すことができる。こ
こでVE は電源電圧、VP は圧電セラミックス1に加わ
る電圧、Vg はガラス層4に加わる電圧を示している。
圧電セラミックス1の静電容量CP はCP =ε0 εP
/dP で表され、ガラス層4の静電容量Cg はCg =ε
0 εg s/dg として表される。ここで、ε0 は真空中
の誘電率、εP は圧電セラミックス1の比誘電率、εg
はガラス層4の比誘電率、dP は圧電セラミックス1の
厚さ、dg はガラス層4の厚さ、sは圧電セラミックス
1とガラス層4の平面積であり、両者1,4の平面積は
等しいので同じ記号のsで表している。
As described above, in this embodiment, the voltage applied during the anodic bonding is not directly applied to the glass layer 4 but is applied to the glass layer 4 via the piezoelectric ceramics 1.
Even if a voltage is applied to the glass layer 4 indirectly via the piezoelectric ceramic 1 as described above, the piezoelectric ceramic 1 has a higher dielectric constant than the glass layer 4, so that a sufficiently high voltage necessary for anodic bonding is applied to the glass. It can be applied to layer 4. This can be explained as follows. An equivalent circuit at the anode junction of this embodiment can be represented as shown in FIG. Here V E is the power supply voltage, V P is the voltage applied to the piezoelectric ceramic 1, the V g shows the voltage applied to the glass layer 4.
The capacitance C P of the piezoelectric ceramic 1 is C P = ε 0 ε P s
/ D P , and the capacitance C g of the glass layer 4 is C g = ε
It is expressed as 0 ε g s / d g . Here, ε 0 is the dielectric constant in a vacuum, ε P is the relative dielectric constant of the piezoelectric ceramics 1, ε g
Is the relative dielectric constant of the glass layer 4, d P is the thickness of the piezoelectric ceramic 1, d g is the thickness of the glass layer 4, s is the plane area of the piezoelectric ceramic 1 and the glass layer 4, Since the areas are equal, they are represented by the same symbol s.

【0018】電源電圧6からVE の電圧が印加される
と、ガラス層4に印加される電圧VgはVg =(1/C
g )VE /{(1/CP )+(1/Cg )}=CP ・V
E /(CP +Cg )=(εP /dP )VE /{(εP
P )+(εg /dg )}のように表される。
When a voltage of V E from the power supply voltage 6 is applied, the voltage V g applied to the glass layer 4 becomes V g = (1 / C
g ) V E / {(1 / C P ) + (1 / C g )} = C P · V
E / (C P + C g ) = (ε P / d P ) V E / {(ε P /
d P ) + (ε g / d g )}.

【0019】本実施例の圧電セラミックス1の比誘電率
は1000〜5000であり、ガラス層4の比誘電率εg は約5
であり、圧電セラミックス1の厚さは300 〜500 μmで
あり、ガラス層4の厚さdg は2μmであり、これらの
値を前記Vg を求める式に代入することによりVg の電
圧が求められ、Vg には約電源電圧VE の2/3の電圧
が印加されることとなり、前記の如く、ガラス層4の耐
圧が十分高められることで、電源電圧VE を大きくする
ことができ、圧電セラミックス1を介して電圧を印加し
ても、支障なくガラス層4に高い電圧を加えることがで
きる。
The relative permittivity of the piezoelectric ceramic 1 of this embodiment is 1000 to 5000, and the relative permittivity ε g of the glass layer 4 is about 5
, And the thickness of the piezoelectric ceramic 1 is 300 to 500 [mu] m, the thickness d g of the glass layer 4 is 2 [mu] m, the voltage of V g is by substituting these values into equation for the V g sought, will be 2/3 the voltage of the V g to about supply voltage V E is applied, the as, by the withstand voltage of the glass layer 4 is sufficiently increased, it possible to increase the power supply voltage V E Even if a voltage is applied via the piezoelectric ceramics 1, a high voltage can be applied to the glass layer 4 without any problem.

【0020】なお、本発明は上記実施例に限定されるこ
とはなく、様々な実施の態様を採り得る。例えば、上記
実施例では無機接着層としてガラスを用い、基板2の材
料としてシリコンを用いたが、これら無機接着層と基板
の材料は陽極接合が可能な材料ならば他の材料であって
もよい。
The present invention is not limited to the above embodiment, but can take various embodiments. For example, in the above embodiment, glass was used as the inorganic adhesive layer and silicon was used as the material of the substrate 2, but these inorganic adhesive layer and the material of the substrate may be other materials as long as they can be subjected to anodic bonding. .

【0021】また、本実施例で示した接合温度および印
加電圧の値は何ら本発明を限定するものではなく、他の
接合温度や印加電圧により陽極接合を行なうことができ
るのは当然のことである。
The values of the junction temperature and the applied voltage shown in the present embodiment do not limit the present invention in any way, and it goes without saying that anodic bonding can be performed at other junction temperatures and applied voltages. is there.

【0022】[0022]

【発明の効果】本発明は接合温度雰囲気中で無機接着層
に印加する電圧を無機接着層に直接印加することなく、
圧電セラミックスを介して印加するように構成したもの
であるから、無機接着層の耐圧を高めることができ、そ
の分、印加電圧を大きくすることができる。印加電圧を
大きくすることにより、その分、接合温度を下げること
ができるので、熱応力の発生およびその熱応力の内部残
留歪が小さくなるので、圧電素子の内部歪に対する機械
的強度が強くなり、さらに、残留内部歪が小さくなるこ
とに伴って圧電素子の内部歪による特性低下を防止する
ことができるという優れた効果を得ることができる。
According to the present invention, the voltage applied to the inorganic adhesive layer in the bonding temperature atmosphere is not directly applied to the inorganic adhesive layer.
Since the voltage is applied via the piezoelectric ceramics, the breakdown voltage of the inorganic adhesive layer can be increased, and the applied voltage can be increased accordingly. By increasing the applied voltage, the joining temperature can be reduced accordingly, so that the generation of thermal stress and the internal residual strain of the thermal stress become smaller, so that the mechanical strength against the internal strain of the piezoelectric element becomes stronger, Further, it is possible to obtain an excellent effect that a reduction in characteristics due to internal strain of the piezoelectric element can be prevented with a decrease in residual internal strain.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施例を示す構成説明図である。FIG. 1 is a configuration explanatory view showing one embodiment of the present invention.

【図2】本実施例におけるガラス層4の耐圧増大効果を
示す説明図である。
FIG. 2 is an explanatory diagram showing the effect of increasing the withstand voltage of the glass layer 4 in this embodiment.

【図3】本実施例における接合温度と印加電圧との関係
を説明するための等価回路図である。
FIG. 3 is an equivalent circuit diagram for explaining a relationship between a junction temperature and an applied voltage in the present embodiment.

【図4】従来の一般的な陽極接合の説明図である。FIG. 4 is an explanatory view of a conventional general anodic bonding.

【図5】陽極接合を利用した圧電セラミックスとシリコ
ン基板との従来の接合例を示す説明図である。
FIG. 5 is an explanatory view showing a conventional bonding example of a piezoelectric ceramic and a silicon substrate using anodic bonding.

【符号の説明】 1 圧電セラミックス 2 基板 4 ガラス層[Description of Signs] 1 piezoelectric ceramics 2 substrate 4 glass layer

───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7,DB名) H01L 41/22 H01L 41/08 H03H 3/00 H03H 9/00 ──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 7 , DB name) H01L 41/22 H01L 41/08 H03H 3/00 H03H 9/00

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 圧電セラミックスと基板とを接着層を介
して接合一体化する圧電素子の製造方法において、前記
圧電セラミックスの接合面に無機接着層を形成し、この
無機接着層を介して基板と圧電セラミックスとを重ね合
わせ、接合温度雰囲気中で基板と圧電セラミックス間に
電圧を印加することによって圧電セラミックスと基板と
を接合一体化する圧電素子の製造方法。
In a method of manufacturing a piezoelectric element, wherein a piezoelectric ceramic and a substrate are joined and integrated via an adhesive layer, an inorganic adhesive layer is formed on a joint surface of the piezoelectric ceramic, and the substrate is connected to the substrate via the inorganic adhesive layer. A method for manufacturing a piezoelectric element in which piezoelectric ceramics and a substrate are joined together by applying a voltage between the substrate and the piezoelectric ceramics in a bonding temperature atmosphere by superposing the piezoelectric ceramics.
JP26164793A 1993-09-24 1993-09-24 Method for manufacturing piezoelectric element Expired - Lifetime JP3114459B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP26164793A JP3114459B2 (en) 1993-09-24 1993-09-24 Method for manufacturing piezoelectric element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP26164793A JP3114459B2 (en) 1993-09-24 1993-09-24 Method for manufacturing piezoelectric element

Publications (2)

Publication Number Publication Date
JPH0794801A JPH0794801A (en) 1995-04-07
JP3114459B2 true JP3114459B2 (en) 2000-12-04

Family

ID=17364813

Family Applications (1)

Application Number Title Priority Date Filing Date
JP26164793A Expired - Lifetime JP3114459B2 (en) 1993-09-24 1993-09-24 Method for manufacturing piezoelectric element

Country Status (1)

Country Link
JP (1) JP3114459B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5994821A (en) * 1996-11-29 1999-11-30 Matsushita Electric Industrial Co., Ltd. Displacement control actuator
DE10104868A1 (en) * 2001-02-03 2002-08-22 Bosch Gmbh Robert Micromechanical component and a method for producing a micromechanical component

Also Published As

Publication number Publication date
JPH0794801A (en) 1995-04-07

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