JPS5848874A - Multimode test terminal circuit - Google Patents

Abstract

PURPOSE:To obtain a test terminal circuit set up so that three states can be selected by one test terminal by providing the circuit with frequency dividers and latch circuits. CONSTITUTION:A signal from a line 106 is divided by frequency dividers 27, 28 and outputted as a timing signal to a line 110. The signal 110 is supplied to latch circuits 22, 23 as a data signal. When a terminal 26 is floated, the data signals of the latches 22, 23 are signals 110 and their output signals 104 and 105 are H and L respectively. If the terminal is turned to the H level, the data of the latches 22, 23 are turned to H and both the output signals 104, 105 are turned to H and, when turned to the L level, both the outputs are turned to L. Consequently three states can be prepared in an integrated circuit by only one test terminal and three modes can be utilized as a test circuit.

Description

[Detailed description of the invention] The present invention relates to test circuits for monolithic integrated circuits.

Monolithic integrated circuits are generally provided with test circuits to determine whether the integrated circuit itself is good or bad, and to make adjustments when combined with other elements. Conventionally, as an example of a method for creating this test mode, a test terminal 10 is provided in the circuit shown in FIG.
Log L/Hell side, Low level is hereinafter expressed as L level. ) is connected to b. When the test terminal 10f floats, the gate 7 of the inverter 13, which is 1 rebuffed to the MO resistor 11, is kept at 12'eL level, and the output potential 14 of the inverter 13 is set to +VDA.
(On the High level side, below the High level)
(expressed as level). In addition, when a low impedance 4iW signal source external to the integrated circuit is applied and the test terminal 1 is set to +VDD (H level), the potential of the 1gM line 12 becomes almost +VDD, and the output potential 14 of the 51 inverter 13 is set to +VDD (H level). becomes L level. In the conventional test circuit system (focusing on the 140 level), one test terminal requires two circuits.
All it does is create a state. The reason for the fact that only two states can be created for one test terminal is the same even if the pull-down resistor 11 in Fig. 1 is replaced with a pull-down resistor (Jt). It is necessary to prepare a large number of test terminals, but providing a large number of terminals is a huge loss for integrated circuits, and when assembling them into a circuit block or package during IrTl, the number of test terminals is generally large. Because it is limited, it becomes a problem for dogs.

In order to alleviate such problems, the present invention provides a method for selecting three states f for one test flame. FIG. 2 shows an example of one circuit, and this circuit example will be explained in detail below.

In the circuit diagram of FIG. 2, signal 106 is connected to the clock of frequency divider 27, and the output of frequency divider 27 is connected to the clock of frequency divider 28. One of the outputs of the frequency divider 27, Q110, is connected to the gate of the impurity converter 21. The output 101 of the inverter 21 is connected to the terminal 26 and the data of the latch circuits 22 and 23. The signal line 10 is internal to the frequency divider 27.
The force connected to the second gate of 8 Kenoa gate 24.25 is ru. Signal 110 is connected to the first gate VC of NOR gate 24. Signal line II inverted from ifiM110
A power is connected to the first gate of the IH terminal gate 25. The signal xo2u of the NOR gate 24 is connected to the clock.

The Ig signal 103 of the NOR gate 25 is connected to the clock of the latch 23.

The operation of the circuit shown in FIG. 2 will be explained below together with the timing chart shown in the m3 diagram. In Figure 2, 4 symbol line 10
If the signal 6 is the timing signal of QN- in FIG. Get out. This QN m-1110 passes through the inverter 2J, which is a buffer, and becomes the data bias of the latch circuit 22.23. Therefore, when the terminal 26 is floating, the data signal of the latch circuit 1322123 of 4-
It serves as a timing signal. The signal 108 is the third
This is the timing signal of M N-1 in the figure, and the signal 1
10 is the timing signal of QN in FIG. 3, and signal 1
11σ The timing of QN in Figure 3 is sharp.

Therefore, the output signal of the NOR gate 24 is equal to the timing signal A in FIG. 3, and the output signal of the NOR gate 25 is
This is the timing signal B in FIG. 3. From the above, if the terminal 26 is lifted, the latch 22.2
The data signal 3 is the timing signal of QN in FIG. 3, the clock of the latch circuit 22 is the timing signal of A in FIG. 3, and the clock of the latch circuit 23 is the timing signal of QN in FIG.
It becomes the timing signal for B of SO.7. QN+ here
7) Paying attention to the relationship between the signal and the signals of A and B, when the signal of A is at H level, Q and N are always at H level, and 4'
When the number 1 of LB is at H level, QN is always at L level. Therefore, when floating the terminal 26, the latch 22
The output signal 104 is always at H level.
The output coefficient of 5-105 is always at L level.

Next, when the inverter 21 is set to an H level at the external terminal 26 of the 4W circuit using a signal source with sufficiently low interference, the signal 101. Since the data of 1 Lira Sochi 22.23 is always at H level, the output signal 104. ．． 1.05 both end at H level.

In addition, when the inverter 21 is set to an L level with a signal source having a sufficiently low impedance, the signal 101
, 1 Lira Sochi 22.23 data is always at L level.

So Eri, H level f1 + L level? If we organize the state of 22 and 23 inside the integrated circuit as 2 bits in correspondence with 0, when terminal 26 is lifted, fist e...(1,0) terminal 26
When set to H level... (1, 1,) terminal 26'eL
When set to level...(0,0). Therefore 1
Three states can be created inside the integrated circuit using five test terminals, and three modes can be used as a test circuit.

6- The above was explained using the circuit example in Figure 2, but this is simple &, l'
-Example: 2-C, 3-mode test☆11 The essence of the circuit is a buffer.
When the 671N latch circuit 22.23 sends the take signal and the terminal 26 is floated, the latch 22.23's chitai FJj÷101 will ensure that the clock Itami 102 is at H level It, '+' t-. Hl/bell is sharp, and when the clock 4.4-4103 is Hl/bell, it is selected at the timing when Jru is ＼＼TJ/bell,
If the timing relationship is maintained, (tt't switch to the lit circuit 1j1).An example of a circuit other than the circuit shown in FIG. 2 is shown in FIG.

In the circuit shown in FIG. 4, the 4IT signal 207 is connected to the clock of a 2-bit TELAY-type flip-flop 37. Haku+'F21161': i-thi・
A type flip-flop 370 is connected to the gate of the inverter 31. Output 201 of inverter 31
(Connected to the goshuko 36 and the latch circuits 32 and 330
1 has been done. (Tiley type) 11 1-bit delay aT of the flop 37 is connected to the first gate of the tour end gate 34. 2-bit delay signal 21 of Tilley-type flip-flop 37
0 is connected to the first gate of the NOR gate 35. The signal 209 obtained by inverting the signal 208 is the NOR gate 35
is connected to the second gate of The signal 211 obtained by inverting the signal 210f is connected to the second gate of the NOR gate 34 (8).

) The output signal 202 of the completion gate 34 is connected to the clock of the latch circuit 32. Output signal 2 of Noah gate 35
03 is connected to the clock of the latch circuit 33 (8).

In this circuit configuration, the signal line 207 is connected to the signal line 20 shown in FIG.
7 timing signal, and the 5th timing signal on double line 206.
When the timing signal 206 in the figure is applied from inside the integrated circuit, each circuit signal in FIG. 4 operates according to the timing signal corresponding to the error number in FIG. 5.

At this time, as can be seen from the timing chart of FIG. 5, when the gate signal 202 of the latch circuit 32 is at the H level, the data signal 201 is always at the H level.

``Furthermore, when the gate signal 28-03 of the latch circuit 33 is at H level, the data signal +: 201 i, 1 is always l/bell. For this reason, the states of the outputs 204 and 205 of the latch circuit are changed to (1,0) and (1,1 ), (0,0) can be created.

In addition, the explanation 1-7 in Fig. 2 shows the frequency dividing circuit 27゜28.
A specific example of the circuit configuration is shown in FIG.

FIG. 7 shows a specific example of the circuit configuration of the latch circuits E22 and E22 in VC in FIG. 2 and the latch circuits 32 and 33 in FIG. 4.

FIG. 8 shows a specific example of the circuit configuration of the two-pit delay type flip-flop shown in FIG. 1 and FIG.

[Brief explanation of the drawing]

1 shows an example of a conventional test terminal circuit, FIG. 2 shows an example of the II-al circuit configuration of the present invention, and FIG.
9 is a timing chart of the circuit shown in FIG. 2, and FIG. 4 is a timing chart of the circuit shown in FIG. FIG. 7 is a diagram showing a specific circuit example of the frequency divider used in FIGS. : is a diagram of a specific circuit example of a latch circuit, and FIG. 8 is a diagram of a specific circuit example of a latch circuit.
This is part 1 of a specific circuit example of a one-tube flop. 21-4 inverter serving as a buffer 22.23: latch circuit, 24.25: gate circuit 26 consisting of -)
...Terminals 27, 28--Frequency divider circuits 104, 105--Latch circuit output or above Applicant Suwa Seiko Co., Ltd. 10-

Claims (1)

[Claims] In a monolithic integrated circuit, there is a buffer signal that sends out No. 4i to a terminal that is an entrance/exit for signals to and from the outside of the integrated circuit, and a signal that is used as input data, and one when the signal is High.
The gate opens at the timing of the level, and on the other hand, the signal is T.
Two latch circuits whose gates open at J o vt level timing and a gate circuit that generates the gate timing are set to H (gh level) by a low impedance signal source outside the integrated circuit. Lo
The IC is configured to create three states inside the integrated circuit using the output signals of the two latch circuits inside the integrated circuit. Features a multi-mode test terminal circuit. 1]-