JPS584849B2 - Warmer body warmer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a step-out detection circuit for a phase-locked oscillator (PLO), and particularly to a step-out detection circuit suitable for a phase-locked oscillator (PLO) with a wide frequency change range used in variable frequency inverters for motor drives, etc. Regarding a detection circuit.

Recently, phase-locked oscillators (PLOs) have come to be widely used as the heart of control circuits not only in the fields of data communication and information processing, but also in the field of industrial equipment.

However, the stable state of the phase-locked oscillator is not limited to just one point, and the output signal may have a frequency that is twice or 1/2 times that of the input signal.

If the equipment is operated in such a step-out state, not only will the equipment not function properly, but it may also lead to a major accident.

For this reason, a method has been devised for detecting such step-out using a step-out detection circuit of a phase-locked oscillator.

FIG. 1 shows a conventional example of such a step-out detection circuit, which is disclosed in Japanese Patent Application No. 49-81058.

FIG. 1 shows a flip-flop 2A made up of two NAND gates 1A and 1B, a phase-locked oscillator 6 made up of a filter 3, a voltage/frequency converter 4, and a frequency divider 5, and external resistors 8A and 8B. A step-out detector is shown comprising two pulse stretchers 7A, 7B having capacitors 9A, 9B, an inverter 10, and a flip-flop 2B comprising two NAND gates 1C, 1D.

The out-of-step detector shown in Figure 1 uses a method that detects the output frequency as normal when it is within a predetermined band, and as abnormal when it is out of the specified band. The characteristics are shown in FIG. 2a for fixed frequency operation and in FIG. 2b for variable frequency operation.

As shown in Figure 2a, when operating at a fixed frequency or when the operating frequency range is very small, the width of the detection frequency (2Δf) can be made sufficiently small to prevent step-out of the phase-locked oscillator. Can be reliably detected.

However, when the operating frequency changes widely as shown in Figure 2b, the detected frequency range changes from fomin-Δf to fomin-Δf.
ax−Δf, which becomes very wide.

(FOMIN is the minimum operating frequency, FOMAX is the maximum operating frequency) For example, when a phase-locked oscillator is used as a control circuit for a variable frequency inverter for controlling a motor, the frequency change range may be about 10 times as large. If a step-out occurs at an intermediate frequency, it is impossible to detect it.

Therefore, the object of the present invention is to eliminate the above-mentioned drawbacks of the conventional system,
It is an object of the present invention to provide an escape detection circuit for a phase-locked oscillator that can reliably detect step-out of a phase-locked oscillator having a wide usable frequency range.

The above object of the present invention is to input a set input, a reset input, and an output from the flip-flop to a flip-flop in a phase-locked oscillator, and to reset the flip-flop when a set signal is input when the flip-flop is in the set state or when the flip-flop is in the reset state. The phase-locked oscillator step-out according to the present invention is characterized in that when a signal is input, that is, when the set input and reset input of the flip-flop are not applied alternately, a signal indicating step-out of the phase-locked oscillator is generated. This can be achieved by a key detection circuit.

Hereinafter, embodiments of the present invention will be described in detail based on FIGS. 3 and 4.

FIG. 3 shows an embodiment of a step-out detection circuit for a phase-locked oscillator according to the present invention, and shows the same phase-locked oscillator 6 as the phase-locked oscillator in FIG. 1 and the step-out detection circuit according to the present invention. ing.

The step-out detection circuit shown in FIG. 3 consists of two NAND gates 1C.
, 1D, and an inverter 1.
0A, 10B, 10C, 10D, 10E and resistor 12
The delay circuit 11 includes a capacitor 13, and NAND gates 1E, 1F, and 1G, and signals of each part are indicated by A to G.

Two input signals A and B to flip-flop 2A of phase-locked oscillator 6 and one output signal C of flip-flop 2A are taken out by inverters 10C, 10D, and 10A, respectively.

The output of the inverter 10A is input to a delay circuit 11, and a signal D delayed by a predetermined fixed time is output.

Fixed time delayed output signal C of flip-flop 2A
and the inverted signal of the input signal A of the flip-flop 2A are input to the NAND gate 1E, and a signal E indicating the result of comparison between the two is output.

On the other hand, a signal D obtained by inverting the output C of the flip-flop 2A and delaying it by a fixed time and the other inverted input B of the flip-flop 2A are input to a NAND gate 1G, and a signal F indicating the result of comparison between the two is output.

The outputs E and F of the two NAND gates are input to an AND circuit consisting of a NAND circuit 1F and an inverter 10E, and the AND signal is input to the set input of the flip-flop 2B.

When this set input becomes a low level, the flip-flop 2B is set, and a low-level signal indicating step-out is output to the output G of the flip-flop 2B.

FIG. 4 shows operating waveforms in the embodiment of FIG. 3.

When the phase-locked oscillator 6 is operating normally, the two inputs of the flip-flop 2A in the phase-locked oscillator 6 are:
Input signals are input alternately.

Therefore, at this time, the outputs of NAND gate 1E and NAND gate 1G are both at high level.

However, when the phase-locked oscillator 6 loses synchronization, pulses are not input alternately to the two inputs of the two flip-flops in the phase-locked oscillator 6, but pulses are input to one of the inputs successively.

FIG. 4a shows that of the two inputs of flip-flop 2A,
When an abnormality occurs in the input signal A, FIG. 4b shows a case where an abnormality occurs in the input signal B, respectively.

In the former case, the output E of the NAND gate 1E becomes a low level, in the latter case, the output F of the NAND gate 1G becomes a low level, and in both cases, the output of the NAND gate 1F becomes a high level, and the flip-flop 2B is set, and the flip-flop 2B is set until a reset input is applied, and the signal G becomes low level to indicate to the outside that step-out has been detected.

As is clear from the above explanation, according to the present invention, step-out is detected by checking the input of the flip-flop in the phase-locked oscillator instead of frequency fluctuation, so it is always accurate regardless of the frequency used. Able to quickly detect out-of-step.

In addition, in the embodiment described in detail, an example was shown using a delay circuit composed of a resistor and a capacitor, but this delay circuit guarantees a delay time equivalent to the input pulse width to a flip-flop in a phase-locked oscillator. For example, a monostable multi-vibration brake can be used.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an example of a conventional step-out detection circuit for a phase-locked oscillator, and FIGS. 2a and 2b are characteristic diagrams showing its operating characteristics. FIG. 3 is a circuit diagram showing an embodiment of a step-out detection circuit for a phase-locked oscillator according to the present invention, and FIGS. 4a and 4b are timing charts showing operating waveforms of various parts of the circuit. Explanation of codes, 1, 1A, 1B, 1C, 1D, 1E, 1F
, 1G...Nand Gate, 2A, 2B...
...Flip-flop, 3...Filter, 4.
...Voltage/frequency converter, 5... Frequency divider, 6... Phase-locked oscillator, 10A, 10B, 1
0C, 10D, 10E... Inverter, 11.
...Delay circuit.

Claims (1)

[Claims] 1. A delay circuit that delays the output of a flip-flop in a phase-locked oscillator that alternately receives a set input and a reset input during normal operation by a predetermined period corresponding to the pulse width of the set input and the reset input; an output of a circuit and two inputs to the flip-flop, and when the set input signal is input when the flip-flop is in a set state, or when the reset signal is input when the flip-flop is in a reset state. A step-out detection circuit for a phase-locked oscillator, sometimes comprising a logic circuit that outputs a signal indicating step-out of the phase-locked oscillator.