JPS59219026A - Asynchronism detecting system - Google Patents

Abstract

PURPOSE:To detect the asynchronism of a PLL circuit with small-scale circuit constitution by providing a voltage discriminating device identifying an asynchronous voltage and a memory storing this discriminated output to an output of a phase difference detector of a phase locked loop. CONSTITUTION:When the input to the PLL circuit is interrupted and the circuit becomes asynchronous state, an output of a phase difference detector PD2 goes to an upper limit voltage VH or a lower limit voltage VL, an output frequency of the PLL circuit becomes respectively an fH or over or an fL or below representing out of synchronism. When the asynchronous state is reached because of a failure in the phase synchronizing loop of the PLL circuit, an output of a PD2 is oscillated in a beat frequency of two frequencies inputted to the PD2 between the voltages VH and VL via a 1/n frequency divider 1 and a 1/m frequency divider 5. The voltage discriminator 7 identifying that the output voltage of the PD2 goes to the voltage VH or VL is provided and if an output of the discriminator 7 becomes an output representing the asynchronous state even once, this output is stored in a memory 8 and the asynchronous state is detected by this stored content.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of Origin 1 The present invention relates to an asynchrony detection method capable of detecting asynchrony of a phase-locked circuit with a small-scale circuit.

(b) Prior Art and Problems No. 11.1 is a block diagram of a phase locked circuit, and FIG. 2 is a block diagram of a conventional asynchronous detection method.

11d1/n frequency divider, 2 is phase difference detector (
3 is a low frequency P filter (hereinafter referred to as LPF), 4 is a voltage plane I-type oscillator (hereinafter referred to as Vco)
, 5 is an 11/m frequency divider, and 6 is a frequency majority voting circuit.

A PLL circuit has a function of generating an output signal that is phase-synchronized with an input signal, and is widely used in consumer electronics communication equipment and the like. The configuration of a PLL circuit is generally as shown in Figure 1.
PD2. LPF3. It consists of VCO4 and frequency dividers 1 and 5, and PD2 receives the input signal (a signal divided by l/n frequency divider 1 and the output signal f17 of VCO4, and a signal divided by Q by m frequency divider 5. Compare the phase with that and output the full error voltage corresponding to the phase difference (where m and n are natural numbers).
This error voltage is smoothed by the LPF 3 and becomes a control voltage for the VCO 4.

As a result, an output signal whose phase is synchronized with the input signal is obtained.

However, even if the PLL circuit is in an asynchronous state, the output level is the same as when it is synchronous, so whether it is synchronous or asynchronous, P
It is difficult to distinguish in the latter stage of the LL circuit. For this reason, conventionally, as shown in Figure 2, one main PLL circuit has at least two (odd number in total) spare PLL circuits that are the same as the main PLL circuit.
Frequency majority vote l'11 j','+ (calculate by i and main I) L
If the output frequency of the L circuit is lower than the majority decision, the main P
The LL circuit detects asynchronization by determining that it has become asynchronous. However, this conventional method has the disadvantage that the circuit size becomes large.

(cl Purpose of the Invention In view of the above-mentioned drawbacks, the purpose of Honkikari 1 is to
) The aim is to promote an asynchronous detection method that can detect asynchrony in L and L circuits.

(d) Structure of the Invention In order to achieve the above-mentioned object, when the PLL circuit is out of synchronization due to input interruption, the output of the PD becomes the upper or lower limit of the output voltage of the PD, and the phase-locked loop is activated. Focusing on the point that when the PL and L circuits are out of synchronization due to an abnormality, the PD output oscillates between the upper and lower limit voltages at the beat frequency σ of the two frequencies input to the PD, Voltage to identify voltage, 4-1] Fixed profit and said 74L
If the output of the pressure determiner becomes an output indicating non-uniform Jt, II, or wide even once, a memory is used to store this output, and the output of the memory is used to detect asynchrony.

(e) Examples of the invention One embodiment of the present invention will be described below with reference to the drawings.

Fig. 3 is a block diagram showing the concept of the asynchronous detection method of the present invention, Fig. 4 is a characteristic diagram showing the relationship between the output π of the PD during asynchronous time and the output frequency of the PLL circuit, and Fig. FIG. 2 is a block diagram of a circuit of a voltage regulator and a memory according to an embodiment.

Components in the figure that have the same functions as those in FIG. 1 are indicated by the same symbols.

7 is a voltage judge, 8 is a memory, 9 to 11 are not circuits,
12 is a NOR circuit, 13 to 15 are NAND circuits, 16 is a memo l), R, ~1 (5 is a resistor, sw is a switch, VDD
vcc indicates voltage.

When the PLL circuit becomes unsynchronized due to an input disconnection, the output frequency of PD2 (-1: becomes the upper limit voltage VH shown in Figure 4). The blade frequency of will be less than the out-of-synchronization fL.Also, if the PLL circuit becomes out of synchronization due to an abnormality in the phase-locked loop, the output of PD2 will change between the upper limit voltage vH and the lower limit voltage VL shown in Fig. 4 by 1/n. Frequency dividers 1 and 17 Vibrate at the beat frequency of the two frequencies input to 1) D2 via m frequency divider 5. Therefore, in the present invention, as shown in FIG. 3, <output of PD2? L voltage is the upper limit voltage ■ H lower limit voltage E
In addition, a voltage judger 7 is installed to identify that the voltage has become E vL. B. A memory 8 is provided to store the output of the pressure determiner 7 even once indicating an asynchronous state, and the asynchronous state is fully detected based on the stored contents that have become asynchronous.

An example of the circuit configuration of the "h; pressure 't" IJ regulator 7 and memory 8 will be explained in the 51st step. In Fig. 5, resistances R4 to R
The value of 4 is determined as follows.

(VDD-VL')
voltage, ■11' is a voltage that is smaller than the upper limit voltage in Fig. 4, vth is the threshold voltage of knot circuits 9 and 1o, and each 'i
As shown in Figure 4, the relationship between Li pressure is as follows (VDD>VH>VH'>VL'> VL
> If you select the resistors R0 to R4k as above VCC0, the PLL circuit in Fig. 3 will be asynchronous and 0PD2
When the output voltage of the circuit becomes VH, the output of the not circuit 1o becomes 0 level, the output of the υf8 circuit 11 becomes level, and
When the output voltage of D2 reaches vL, the output voltage of the knot circuit 9 reaches a level. The output of hlc p noate 12 is 0 when abnormality occurs. It is 1 under normal conditions. This resulted in an out-of-synchronization state, which caused another problem with kuX. Next, the memory 16 will be explained. The input e of the NAND circuit 13 is normally set at 0 level. The relationship between the levels of points a, b, C, and d of the memory 16 is as shown below. When normal, point C is at 5 level and level C is 0 level, and when abnormality occurs, point C is level at bAFio level.

Normal time d=1 a, ~1 b=1 c=0 Abnormal time d=Oa=1 b =Oc ~1Next, even if the output of PD2 is the normal voltage, it will be 5 points as shown below. is 0 level C point idl level - or 1.

Normal voltage d=1 a=1 b=Oc=1 So, for example cA or fc, connect a light emitting diode to point d JD, r #
;j: If you do this, even one ship will have an unsynchronized voltage I)
If G1] is generated from D2, the light emitting diode will emit light, and all asynchronous states due to input disconnection and phase-to-phase loop abnormality can be detected. jnil level and is reset. By providing a small-scale voltage detector and memory in this manner, asynchronous full detection is possible.

(f) J: #+'As will be explained in detail, according to the present invention, there is an effect that all asynchronous PLL circuits can be detected with a small-scale circuit 444.

Easy success on the 41y-1 plane Figure 1 is a block diagram of a phase-locked circuit, Figure 2 is a block diagram of a conventional asynchronous detection method, and Figure 3 is a block diagram showing the entire concept of the asynchronous detection method of the present invention. Figure, 41st! '411
i Asynchronous time 4LI difference detector output voltage and phase interval Jυ”
Custom-made diagram showing the relationship between the output LtI frequency of the turning tile, No. 5
The figure is a block diagram of the circuit of the '-mountain specific pressure determiner and memory of the embodiment of the present invention.

In the figure, 1 is a 1/n frequency divider, 2 is a phase difference detector, 3 is a low-frequency P-wave device, 4 is a '■L pressed 1-node J-shaped oscillator, and 5 is a 1/m
Frequency divider, 6 is frequency majority decision circuit, 7 is courtesy, Ohanwashiki, 8
．． 16 is a memory, 9 to 11 are NOT circuits, 12 is a NOR circuit, and 13 to 15 are NAND circuits 'J? z, 1-R, 5 are resistances, S'vV is a switch ○Yo 3rd mouth 4th mouth VeCVL VHVDD air pressure

Claims (1)

[Claims] If the output of the phase difference detector of the phase synchronization 11 path is out of synchronization, and the voltage determiner that identifies the pressure and the output of the voltage determiner become an output indicating an unsynchronized state even once, this will occur. An asynchronous detection method that includes a memory that records the output, and detects asynchrony based on the output of the memory.