JPS5848292A - アドレス・バツフア回路 - Google Patents

アドレス・バツフア回路

Info

Publication number
JPS5848292A
JPS5848292A JP56145465A JP14546581A JPS5848292A JP S5848292 A JPS5848292 A JP S5848292A JP 56145465 A JP56145465 A JP 56145465A JP 14546581 A JP14546581 A JP 14546581A JP S5848292 A JPS5848292 A JP S5848292A
Authority
JP
Japan
Prior art keywords
inverter
signal
stage
latch
buffer circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56145465A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0157432B2 (enrdf_load_stackoverflow
Inventor
Hideaki Ito
伊藤 英朗
Atsushi Suzuki
敦詞 鈴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56145465A priority Critical patent/JPS5848292A/ja
Publication of JPS5848292A publication Critical patent/JPS5848292A/ja
Publication of JPH0157432B2 publication Critical patent/JPH0157432B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C8/00Arrangements for selecting an address in a digital store
    • G11C8/06Address interface arrangements, e.g. address buffers

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Static Random-Access Memory (AREA)
JP56145465A 1981-09-17 1981-09-17 アドレス・バツフア回路 Granted JPS5848292A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56145465A JPS5848292A (ja) 1981-09-17 1981-09-17 アドレス・バツフア回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56145465A JPS5848292A (ja) 1981-09-17 1981-09-17 アドレス・バツフア回路

Publications (2)

Publication Number Publication Date
JPS5848292A true JPS5848292A (ja) 1983-03-22
JPH0157432B2 JPH0157432B2 (enrdf_load_stackoverflow) 1989-12-05

Family

ID=15385862

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56145465A Granted JPS5848292A (ja) 1981-09-17 1981-09-17 アドレス・バツフア回路

Country Status (1)

Country Link
JP (1) JPS5848292A (enrdf_load_stackoverflow)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6252793A (ja) * 1985-06-20 1987-03-07 エスジーエス―トムソン マイクロエレクトロニクス インク. 低電力動作アドレスバツフア
JPH0289292A (ja) * 1988-09-26 1990-03-29 Toshiba Corp 半導体メモリ
JPH02105392A (ja) * 1988-10-14 1990-04-17 Nec Corp 半導体メモリ装置

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6252793A (ja) * 1985-06-20 1987-03-07 エスジーエス―トムソン マイクロエレクトロニクス インク. 低電力動作アドレスバツフア
JPH0289292A (ja) * 1988-09-26 1990-03-29 Toshiba Corp 半導体メモリ
JPH02105392A (ja) * 1988-10-14 1990-04-17 Nec Corp 半導体メモリ装置

Also Published As

Publication number Publication date
JPH0157432B2 (enrdf_load_stackoverflow) 1989-12-05

Similar Documents

Publication Publication Date Title
US6211704B1 (en) Asynchronous sensing differential logic (ASDL) circuit
US4710650A (en) Dual domino CMOS logic circuit, including complementary vectorization and integration
KR100193056B1 (ko) 동기회로
US5867049A (en) Zero setup time flip flop
JPS5925421A (ja) 同期式論理回路
US6922083B2 (en) High speed sampling receiver with reduced output impedance
US6563357B1 (en) Level converting latch
US8736340B2 (en) Differential clock signal generator
US20030080793A1 (en) Flip-flops and clock generators that utilize differential signals to achieve reduced setup times and clock latency
JPH0338873A (ja) 集積回路
US5751176A (en) Clock generator for generating complementary clock signals with minimal time differences
JPH11177639A (ja) データ伝送装置
KR100741561B1 (ko) 래치, 및 d형 플립플롭
US7161992B2 (en) Transition encoded dynamic bus circuit
US5155382A (en) Two-stage CMOS latch with single-wire clock
JPS5848292A (ja) アドレス・バツフア回路
US20010015665A1 (en) Synchronous type flip-flop circuit of semiconductor device
JPH1173775A (ja) 半導体記憶装置の出力回路
US4741005A (en) Counter circuit having flip-flops for synchronizing carry signals between stages
JPH05206791A (ja) D型フリップフロップ
EP0282924B1 (en) Bipolar with eight-zeros substitution and bipolar with six-zeros substitution coding circuit
JPH1093397A (ja) D型フリップフロップ
US6212125B1 (en) Asynchronous semiconductor memory device with a control circuit that controls the latch timing of an input signal
US7202703B2 (en) Single stage level restore circuit with hold functionality
CN105048998B (zh) 冗余时钟转变容限锁存电路