JPS5848292A - Address buffer circuit - Google Patents

Abstract

PURPOSE:To reduce the scale of an address buffer circuit, by securing the synchronism just with a latch signal for a clock synchronizing C-MOS address buffer circuit having the reduced power consumption. CONSTITUTION:A clock synchronizing C-MOS address buffer circuit contains a first stage inverter 1, the next stage inverter 2 and an FF3. The power consumption of such buffer circuit is reduced with use of the latch signal that activates the inverter 1 only for a period during which the input address signal AIN is latched. Furthermore this latch signal is used to secure the clock synchronism between the inverter 2 and the FF3. Then the mutual conductance of the transistors forming the inverter 2 is set larger than that of the transistors forming the FF3 to assure the latching action of the FF3. In such way, the synchronism is secured only with the latch signal. This can reduce the scale of an address buffer circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides complementary 1! Regarding address buffer circuits suitable for use in MO8 (0MO8) RAMC random access memory)K, generally %C-MO8-RA
The latch type address buffer @II in MK is C
The input address signal is latched from the PU (central processing unit)* via the C-MO8 inverter in synchronization with the rip-tuk signal, and the latched address signal is output to the input address signal via the decoder.・Used for cell addressing. As is well known, the C-MO8 inverter is constructed in such a way that a p-channel transistor and an n-channel transistor are connected in series and an input signal is commonly applied to the gates of these transistors. Since there is no direct current path other than the leakage current R when it is at rest and is in a conductive state, the current consumption at this time is several liters of ohm.
However, the potential level of the input address signal of the C-MOS address/parameter circuit is not guaranteed to make only one transistor conductive. At least C-MO8O8 depending on the level of the input address signal
Address Paratour first stage inverter, maximum several lo
For example, in the case of a 4-bit RAM, a DC-like current of OsA II variation may flow, and the current consumption mAK due to this DC current is slow, and the characteristics of the C-MO8 device are impaired. - In order to reduce the above-mentioned power consumption at the first stage inverter of the C-MO9 address/parameter circuit, we have filed a patent application No. 54-165232 filed on December 19, 1978.
K. proposed an address/parameter architecture with an additional clock circuit that generates an O-latch signal in order to operate the first-stage inverter only during the period when the input address signal is latched.

By using this latch signal, the first-stage inverter does not operate outside of the latch period, so regardless of the level of the input address signal, the direct current flowing through the first-stage inverter becomes zero, significantly reducing power consumption. Ta.

However, according to the above-mentioned prior art by the present applicant, in addition to the four-way synchronization, the latch signal has been conventionally used to generate a 7-lip 70-tub tS for the middle of the next-stage inverter. In other words, clock synchronization must also be performed using a clock signal and its inverted signal.

The problem is that the space/parameter circuit connection and stomach synchronization must be performed using three-phase clock signals, and therefore one path that generates three-phase clock signals is required, resulting in a large circuit scale and high equipment cost. In view of the problems in the prior art described above, the purpose of the present invention is to provide a latch signal that operates the first stage inverter only during the period when input address notes are latched, and also performs vine synchronization in the evening of the next stage inverter.
And the mutual conductance of the transistors constituting the next stage inverter, the mutual conductance gmj of the MO8 transistor constituting the 7 lip flop for the latch.
Based on the idea of making latching possible without a clock signal on a larger scale, we developed a single-phase C-MOS address buffer circuit that uses a latch signal to reduce power consumption. The purpose of this invention is to reduce the circuit scale (by synchronizing with the glue bag signal) and reduce the cost of the device.Hereinafter, the embodiments of the present invention will be compared with the prior art and the following will be attached.
The explanation will be based on the drawings.

1115cl is a conventional address buffer circuit (Japanese Patent Application No. 165232/1989) previously proposed by the present applicant.
In the circuit diagram c=I11, which is a circuit diagram shown in FIG. , and a 7-lip 7o-tube 3 connected to the output terminal N2 of the next-stage inverter 2. The outputs of flip-flops 3 and 2 (17) are output to a decoder (not shown) as output address signals A and A, respectively, via inverters pINV, , INV*. First stage inverter! A p-channel transistor Q constituting the power supply Ye@ and a p-channel transistor Q constituting the power supply Ye@ are inserted. First stage inverter
0 transistor Ql-Q4 in which an n-channel transistor Q4 is inserted between the output terminal Nl and the ground power supply Vsm.
A p-channel transistor Q7 is inserted between the p-channel transistor voltage in the next stage inverter 2 and the power supply Vec, which receives the latch signal φ at its gate. An n-channel transistor is also inserted between the n-channel transistor Q and the ground power supply Vsa to receive the internal inverted four-channel signal φt gate. 7 Ripdrop 3 and Electric If Vc
Similarly, a p-channel transistor Q+t for receiving a one-clock signal φ and a high-channel transistor Qu for receiving a full-clock signal φ are inserted between the power supply e and the ground power source vl.

Fig. 112 shows an internal four-wheel inertia signal φ for driving the next-stage inverter 2 and tree tube flop 3 in the circuit shown in Fig. 1.
This is an internal four-turn signal generation circuit to generate the inverted signal φ. As is clear from the figure, the internal clock signal φ is connected to the input clock signal CEt inverter INV, ~
The internal inverted tally signal 7 is obtained by further passing φ through one stage of inverters INV,1.

@3 Figure is a latch signal generation circuit that generates a latch signal 'It~ for driving the first stage inverter l of the circuit in Figure 111. In FIG. 3, the internal inversion clock signal φ is amplified and waveform-shaped by the inverters INV, , INV, and INV, and the KhP channel transistor Q is connected between the output terminal N of the inverter INV and the power supply Vce.
dJE is inserted, and an n-channel transistor Qz forming the inverter INV.

An n-channel transistor Qz+ is inserted between the power supply and the ground power supply, Vss. Transistor Q8 and Q
The gate of □ is connected to the output terminal N4 of the first stage inverter INV of the 2nd H gate signal generation circuit 0! ! Due to the configuration of the inverter INV, a latch signal that falls for a predetermined delay time from the switching of the internal inverted clock 411 is obtained at the output terminal of the inverter INV. 0 to 113 are waveform diagrams for explaining the operation of the circuits shown in FIG. Internal clock signals φ and φ obtained by the circuit shown in Fig. 2, @4 (e) are latch signals 4I~, 114 - obtained by the circuit shown in @3)
p is the input address signal input to the address buffer circuit shown in Figure 1.

The input address signal at the time when the internal clock signal φ switches from low level to high level - is the valid address signal to be latched.
) is the latched output address signal obtained at the output of the circuit. 1. Inverter I seen in Figure 4 (C)
Transistor Qse (@Fig. 3) is turned off with a delay due to only Nη (Fig. 1142), and transistor Q2
(by turning on 1t), after the falling edge of the internal clock inverted signal φ, the inverter IINV, ~INV
, (11311)K! Therefore, the latch signal ~ is at a low level only during the period when the input address signal is latched. As shown in Fig. 4(f)K, the DC current flowing through the first stage inverter 1tll is substantially zero except during the latch period, and the current xcct which is louder than zero only during the latch period.
W is about. This study results in a significant reduction in power consumption compared to the conventional address buffer 111GK, which does not provide a latch signal.
Next stage inverter! and 7 rip 70 lub 307E1 latch synchronization is O using clock signals φ and - which are different from the latch signal ~, and clock pulse generation I is abbreviated as 11
Requires the complicated route shown in Figures 211 and 113,
There was a problem that the price was high.

The present invention was proposed to solve the problem of ζO.
, I will explain the implementation f1 below.
This is a circuit diagram showing the address pad 7teaIIt based on the actual operation, so in the VXS diagram O circuit, the same parts as in diagram 1111 are marked with the same symbol as in diagram 1111, and as in diagram @1, the first stage inverter 11th order The latch signal "70" used for synchronizing the address pad adopts in FIG. 6 is shown in FIG. Ilatch Shinki
It must be a single-V@V signal obtained from l raw @ path・st
lolllllKM! hbnteeA crisis, next R4yA-p゛! Activate! *Me O transistor fake, 7 lip 71
1yP3Yt Activation Sui Master O) Lungesme CBS-9
1 is unnecessary in the 5110 circuit, and
Next stage inverter! To configure the p-channel transistor voltage and the h-channel transistor IQGO, the 7-channel transistor and the n-channel transistor Q:,
As will be described later, the flip 7Wy is set to be larger than the gm of the next stage inverter 20 so that the flip 3 latches the potential change at the output terminal of the next stage inverter 20.
flN@mn@Sm0YVvx-Py 7 v@Wtt
) is a latch signal generation circuit for clock synchronization to generate four clock synchronization latch signals 4#~, and is basically a latch signal generation circuit for clock synchronization.
It is similar to the circuit shown in Fig. and IK3, but it does not require the internal pck signal and dco formation.
As is clear from the figure, the number of inverters in the circuit 116 and FIG. 1161!1I110 IIK, a latch signal for clock synchronization substantially equivalent to the latch signal shown in FIG. 4 (C) is generated.

Only when the latch signal is at a low level, the first-stage inverter 1 and the next-stage inverter 2 are activated, and the input address signal MU1 is read. At this time, the slip flop 3 checks the potential level f5tp of the output terminal N1 of the inverter 2. This latch operation is caused by the g
m t ) C ensured by making the resistor QG * QC@ 1 m 19 large, that is, the output terminal N of the next stage inverter 2 is now at a high level, and t φ - working height level follows. 71 no? Assume that the output terminal N of the flip-flop 3 is latched to a low level. At this time, the transistor Qss in the 71J tube flop 3 is non-conductive, QS4 is conductive, Q is conductive, and QCs is non-conductive], the transistor q in the next stage inverter 2 is conductive, and QS is non-conductive. Since φ4 is at a high level, Q is non-conductive! Therefore, the output end of the next stage inverter 2 is latched to a high level. Next, when the latch signal 〈〈 is at a low level and the input address signal A is switched from a high level to a low level, NtFs becomes a high level, and the transistor Q in the primary stage inverter 2 becomes non-conductive, and QS When becomes conductive, transistor Q; is also in conduction state, but since the gm of α is larger than the gm of QS, the output voltage becomes low level, and due to the operation of the flop 3, N becomes low level. N3 is at a high level, so the exposure is non-conducting, Q; becomes conductive. When stage 1 in this state changes to a high level, N goes to a low level & so QS is non-conductive% and QG is conductive.

q becomes non-conductive 9, the state of the flop 3 is fixed and the latch is completed, and φ↓ is at a high level.
When the input terminal N3 of the Aritz flop 3 is latched to a high level and outputs LQ, the input address signal A is at a low level.
I) The latch operation when l changes from low level to high level is similarly affected.

As is clear from the above description, according to the present invention, the first stage inverter of a four-clock synchronized C-MOS address buffer circuit can be activated only during the latch period of the input address signal, and the entire address buffer circuit can be This not only reduces power consumption, but also reduces the circuit scale of the address balance circuit and its crotter signal generation circuit, thereby reducing the cost of the device.

Note that the present invention is not limited to the above-described embodiments, and various modifications may be made. For example, the number of inverter stages included in the circuit is a must! ! 0゛ may be increased or decreased as appropriate depending on

[Brief explanation of the drawing]

1ryJ is a circuit diagram showing a conventional address buffer circuit, and Figures 2112I and 3 each show an internal clock signal generation port and a latch signal generation circuit used in the circuit of Figure 1. Circuit diagram, No. 48iil is @iml
The waveform diagram and aS diagram for explaining the operation in Figure 3 are from this source @O-
n schematic diagram showing the address 1 buffer times I@ according to the embodiment,
Figure @6 is a circuit diagram showing a clock synchronization latch signal generation circuit used in the ll5lII circuit. In the figure KTh, l is the first stage impalm 2, the next stage invert/-3 is a flip-flop, φo is a latch signal, and φ. , φHirouchi check signal sA1. t; is an input address signal; A and MU are output address signals; 01 is an input ri-tsuk signal; 4 Patent Applicant Tomitsu Co., Ltd. Patent Application Agent Attorney: Aoki, a Japanese dialect attorney (Japanese) 1) Shino patent attorney, Akiyuki Yamaguchi

Claims (1)

[Claims] 1. In a latch-type address buffer circuit used in a four-way synchronous complementary 11M18 random access memory, the first stage C-MO to which an address signal is input is
S inverter, lll0 transistor inserted between the first stage C-MOS inverter and the power supply, the first stage C-MOS
The output terminal of the S inverter is connected to the next stage C-MOS inverter, the IIE2 transistor inserted between the next stage C-MOB inverter and the power supply, the IIE2 transistor, the Kuugou I and the Part 2 transistor to the input address. It is equipped with a tarlock circuit that generates a latch signal that turns ON ON during the period when the signal O is latched, and an arrest flop connected to the output terminal of the next-stage inverter, and an fmt1m arrester for the transistors constituting the next-stage inverter. By increasing the GM of the transistors constituting the flop, we decided to use only the latch signal as the clock signal.