JPS5848252A - Information reading system - Google Patents

Abstract

PURPOSE:To realize an automatic reproduction of video information accordant to an educational schedule, by obtaining data of high reliability by detecting the lapse of time and reading the data when no reading command is given before the prescribed time elapses. CONSTITUTION:A clock pulse (i) synchronizing with the bit forming a program or data of the reproduction output of a VTR2 is formed by an I/O13 within a computer 3. The pulses (i) are counted 51 at every 1H scanning section, and the data reading command is given to a CPU4 every time the count value reaches the prescribed amount. In case no reading command is given from the I/O13 before the prescribed time elapses after the preceding data is read in, the CPU4 detects the lapse of time and reads in the data. As a result, the data is read in without fail although the data of the reproduction output has a bit dropout.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a video recording medium using a tape-like recording medium! Signal,
In particular, a VTR control system in which a video tape recorder and a microcomputer are combined, program information recorded on a magnetic tape is read by the microcomputer, and the reproduction mode of the VTR is controlled based on this program information. It is most suitable for use.

An educational system using VTRs has been introduced into school education. Such systems typically require V
'l'R was often operated manually, which placed a heavy burden on the educational side. 0 In view of this problem, the present invention combines a computer such as a microcomputer and a video signal reproducing device such as a VTR to provide an educational program that automatically reproduces video information according to the educational schedule. The first purpose is to establish a system. ◎For this purpose, the present invention tries to prevent data reading loss (data dropout) from occurring as much as possible.

Embodiments of the present invention will be described below with reference to the drawings.

The VTRTR control system of this embodiment controls the reproduction mode of the video signal on the video tape based on the video signal on the video track on the video tape and the data information for the CPU' of the microphone. It is configured as follows.

In addition, an address bus is recorded on each track to search the video source recorded on the tape.
The TR control system can be installed, for example, in an educational system at a driving school.

FIG. 1 is a plan view of a video tape (1) used in this system showing information recorded on the tape.

Video source 7° (1) includes video sources Ss, St-Ss, which are classified according to the student's level.
is written.

will be recorded. Adjacent to these video sources are system control programs P1, P2, P3...
... has been written. These programs are loaded onto the microcomputer, and the microcomputer operates according to this program.This allows the entire system to be controlled.Each program includes a program that asks questions to the students, and this question A glogram card that searches for and reproduces the next required information according to the student's answers (manual key operation). It is provided. In particular, the first program P has two other programs P2, Ps...
The information power of the address on the tape! These address data are stored in the microcomputer when the first program is loaded into the microcomputer. A search for necessary information is performed based on this address data.

FIG. 2 is a block diagram of the entire VTR control system. VTR (2+ is a microcomputer (3)
The icroco/i-user (3) takes in the program written on the tape of the VTR (2+), and based on this program, the microcomputer (3) powers the operation of the VTR (21) again. Control.

As is well known, the microcomputer (3) has a CPU (4)
) (central processing unit), ROM (5), RAM (61), data bus (7) that connects this controller, address bus (
8) I am prepared. Also provided is an I10 interface circuit aυ.121 that couples the microcomputer (3) with an external key input device (9) and a printout device Ql. The CPU (41, ROM (5L) of the microcomputer (3) is connected via the I/6 interface circuit (131) equipped with an expansion cargo
It is combined with the RAM (61). A consumer VTR can be used as the VTR+21 without modification.

FIG. 6 is a plan view of the tape showing the track pattern on video chip f(1). Each track on the tape (15
1 is the address 1lllil indicating the absolute address of the track.
is written in each vertical blanking interval. Further, data necessary for programming and control is written with a synchronization signal added in the video signal section.

FIG. 4 is a waveform diagram showing the format of digital data such as addresses and programs recorded on a videotape. In this embodiment, the number of data recording bits in one horizontal section is set to 8 bits, and the CP of the microcomputer (3) is set to 8 bits.
This is the same as the number of pits handled in U (4).

The data is 40μ(6) for one horizontal section as shown in Figure 4.
It is recorded with FM modulation over a range of .

A 1'' of F'M modulated data has a rising or falling transition within one bit, and a tape ``0'' does not have this transition.

FIG. 5 is a diagram showing the data writing format for each field. Each vertical line in FIG. 5 indicates each field forming a raster i of one screen, and each scale indicates a horizontal descendant number. Address data is written over the 12th to 14th horizontal intervals (H) of the vertical blanking interval (V-BLK). Therefore, since the address data is inserted into the no-signal period immediately after the vertical synchronization signal, there is no effect on the playback screen or any slowness. Each address is 3 bytes (8 pits x 6) of data, the first 2 bits are used as sync bits, and the 6th bit is used as a parity check bit for address data. Therefore, the address data itself is 21 bits, which can be used to assign addresses corresponding to about 10 hours' worth of tracks.

"00" indicates normal video information, and r'11'J indicates program information.

Program insertion section p of videotape (1) 4 in Figure 1
2. p,..., the video information recording section S
s, 82... is completed, the program code is executed at intervals of about 32 fields as shown in Figure 5.
A 128-byte dummy program code is written in the 57th H to 184th H of which the write code is the write code. By recording this dummy program, the recording circuit of the VTR (2) is prepared to be able to stably record actual program data.

Enter the field where the program code will be written,
Thinks J in the 57th H? Tar/FF (all 1.16
In the system, Fp) is written. Note that this sync/mother turn is FM modulated as described above during writing, so
! It is recorded as a square wave signal with 8 periods at 200 KHz.

The program code is written in multiple tracks of 128 bytes each, but if there is a reading error in one track, the entire read program will be invalidated.
The same program code is written to each of three consecutive tracks. Therefore, identification codes FNr00Jr01 Jr02J for identifying these six tracks are written in the 58th H following the scene pattern FF.

In order to store the program in the RAM (61) of the microcomputer (3), store address data 8A indicating the start address of the RAM is written in the 59.6th DH next to the identification code. The above store address data SA; CRC code for error detection and error correction is written in 62H and is blank.

Next to the CRC code, data indicating the program length written in one track is written, and then the 64th H~
A 128-byte program code is written over the 191H. This program code constitutes a part of the entire program (for example, 1 byte). Next to the program code is the CRC code (No. 192.193H)
is added, and the recording of a series of program data is completed.

FIG. 6 is a diagram showing the Grodarum writing area node rack on the chip. As mentioned above, 6 tracks 00.0
The same 128-byte program is successively written to each of segments 1 and 02, forming one program segment p. and multiple programs p+, p+
* p-s... An immediate collection constitutes one program block Pn. One program has a length of 256 bytes to 1 byte, and in the case of 256 bytes,
is divided into 128-item segments and written into six tracks each, for a total of six tracks. Further, if 1 byte is written, it is written to 24 tracks.

When reading program data, first read the program data.
The first track of the segment (identification code r O' O
'J'') is read. If there is no reading error, the same program written in the 21st and 6th track will not be read. If there is an error, the second track (
Program reading of code r01J) is performed. Second
If there is a further error in the track, the sixth track (code r O2,J ) is read.

If there is a reading error up to the third track in one program segment, part of the program is lost and the entire program block becomes invalid. Therefore, as shown in the tape plan view of FIG. 7, one program block Pn and the same broadcaster block P
n', Pn'' are written in adjacent areas. If a reading error occurs in the Zoropram segment in one program block Pn, the tape is rewound and the program block Pn is written in adjacent areas. Block Pn' is read.'If further reading failure occurs in this block Pn', rewinding is performed again and the next nogram block Pn' is read.

Figures 8A and 8B are partial plan views of damaged tapes.
In ~4 fields (tracks), there is a high possibility that reading errors will occur in the same horizontal sections indicated by black circles. In addition, in FIG. 8B, reading failures occur in the same horizontal section over a considerably long field, due to scratches in the longitudinal direction of the tape caused by the tape running system. In this case, as shown by black circles, there are fields in which the read cine quality occurs and fields in which it does not occur.

As such a reading failure, the following cases must be assumed. That is, within one field,
A read failure of two or more bytes (two or more horizontal sections) may occur, and these defective bytes may occur continuously in the same horizontal section over about six fields. This read-out defective data spans multiple pits and must be dealt with as missing data (data V dropout) that cannot be corrected. Note that the possibility that consecutive defective data of two or more bytes will occur in the same field is quite low.

Considering this condition, in this embodiment, as shown in FIG. 9A-C, three consecutive tracks (identification codes r00Jr01 Jr02j) on which data of the same content is recorded,
Each piece of data is recorded with a shift. By this operation, even if read cine defects occur in the same horizontal section on six tracks, the probability that the same data will be defective is extremely reduced. Therefore, during reproduction, extremely reliable good data can be extracted using majority logic that detects coincidence of two out of three pieces of data.

Next, writing of video information and program information will be explained. Figure 10 shows I1 of the microcomputer (3).
11 is a block circuit diagram of a data write circuit in the 0 interface circuit (131), and FIG. 11 is a diagram showing its operating waveforms below.

Video No. 4 a to be recorded on the tape (1) is applied to the input terminal αη of FIG. 41-0. This video signal a is sent to a sync tip clamp circuit +181, where the leading edge level of the sync signal is clamped to a predetermined reference level. The runzo pulse required for the 2-amp operation is the synchronizing signal 5YNC in the input video signal a (Fig. 11.A).
is used, and this synchronization signal is obtained by being separated from the video signal a by a synchronization separation circuit H. The clamped video signal is transferred from the switching power terminal (A) to the VTR (2) in Figure 2.
) will be sent to.

Address day to record! and program data are transferred to the data bus (8) of the microcomputer (3) in Figure 2.
Line 8~D7 to iJ? parallel to serial converter (
After being converted into serial data b as shown in FIG. 11F, it is modulated into FM data C shown in FIG. 11G by an FM modulator (c). The FM data C is sent to the synthesis circuit Q through the -AND circuit (2), where a synchronizing signal is added, and then output to the output terminal (A).

Parallel-to-serial conversion and FM modulation are performed at 4MHz obtained from the clock line of the microcomputer (3).
This is done in synchronization with the clock CK. This clock Ck
is supplied to the frequency division and timing control circuit 2, from which the 1/10 frequency divided clock C necessary for FM modulation is supplied.
K1 (Figure 11 B'') and 1/20 frequency divided clock CK2- (Figure 11 D) are sent to the FM modulator (C), and the 1/20 frequency divided clock CK2- (Figure 11 D) is sent to the FM modulator (C), and the 1/20 frequency divided clock CK2- (Figure 11 D) is sent to the FM modulator (C).
The divided clock CK3 (FIG. 11C) is sent to the parallel-to-serial converter (E).

Further, in the frequency division and timing control circuit, a data area signal d shown in FIG. 11E is formed. This data area signal d represents the section in which data is inserted within one horizontal section, and in this section, the FM modulator (
C) is sent to the FM modulator IN- to operate. In addition, this data area signal d is sent to the microcomputer via the sofa (E) as an instruction signal to send the next data at the end of the data writing to the VTR.
(3) to the data bus (8). The data bus (8) of the microcomputer (3) is supplied with a vertical synchronization signal V-8YN output from the synchronization separation circuit Ql in order to create address data for recording tracks in the computer.
C is given via a buffer (c).

The address data and program data to be recorded are FM modulated by the FM modulator (Incorporated) as described above, and then sent to the synthesis circuit Qη via the AND gate (c). Since the FM modulator always operates in the section of the data area signal d in Fig. 11E, even in the section where there is essentially no data, data 1
An output corresponding to IOj is formed. If this is recorded as is, it will be difficult to distinguish it from the original data "0". For this reason, ANDf-) (c) is opened and closed to prevent FM modulation data from being recorded in the no-data section. The opening and closing of the AND gate (c) is performed based on the output of the RS flip float (e). This Fritsuno flop handle converts the address data (addresses used in the computer) supplied via lines A7 to A7 of the address bus (7) of the microcomputer (3) into codes at the address decoder (to). It is set and reset by signals 80H and 81H (hexadecimal numbers). The address decoder is also the address information given from the CPU (4) to the RAM (61) when recording data is loaded onto the data bus (8) in the microcomputer (3).

The program data and address data sent from the AND gate (E) to the synthesis circuit (21) are added with a synchronization signal and sent to the VTR (2) as a television signal. That is, as shown in FIG. As shown, the synchronization signal 5YNC from the external input video signal a is extracted in the synchronization separation circuit a9. Which synchronization signal is supplied as a clear signal to the frequency division and timing circuit (A) via the horizontal separation circuit Gυ. At the same time, the level impedance converter (34) is connected to the sink clamp circuit 05.
Sent to 1. This sync tip clamp circuit c35)
is given the same flange potential as the sync chip clamp circuit on the video input side described above. Therefore, the output of the clamp circuit (to) has its synchronization tip clamped to the same level L as the video signal to be recorded, as shown in FIG. 11H. The output of this clamp circuit C35) is
It passes through the selector switch (to) and is sent to the synthesis circuit (c).
It is added to the recording data C as shown in FIG.

According to this recording method, the recording traces of the synchronization signal on the tape are completely aligned between the video recording section and the data recording section. Therefore, the VTR (2) performs recording operations stably,
Also, the playback operation is stable.

The switching of the changeover switch (a) is controlled by the output of a toggle type fritsofflop (to) which receives the output 82H (in hexadecimal notation) of the address decoder (to). That is, when a video signal is recorded, the changeover switch (a) is connected to the contact point (20b) in the 1st to 14th horizontal sections and the 275th to 277th horizontal sections, and a synchronization signal is sent to the track address data. is added. When program data is recorded, the changeover switch (a) is connected to the contact (20b) about 62 fields before the program data recording field, as described above.

In the manner described above, the videotape (1) shown in FIG. 1 is created. All information recording onto the tape (1) is controlled based on the program of the microcomputer (3). An example of the program is as shown in the flowchart of FIG. 12, for example.

Well, the microcomputer first receives the vertical synchronization signal V.
-Waiting for the arrival of 8YNC, judgment 100 in Figure 12
When the arrival of V -5YNC is detected at 600μ
A delay process 101 is performed and address data is written (process 102). Next, in judgment 106, the track - another code FN
If F'N=00, delay processing 106 is performed and program data is written (process 107) as shown in FIG. 9A. If rN=01, delay processing 105 and 106 are performed, and program data is written with a delay amount of 2 as shown in FIG. 9B. If FN=02, delay processing 104 to 106 is performed, and Write program data with a delay amount of 6 as shown in C. As a result, shifted recording is performed.

To write address data and program data,
This is performed in the approximately 40 μs data region of FIG. Therefore, the opening and closing of the AND gate (in FIG. 10) is controlled as shown in the flowchart in FIG. 16.

In other words, in the judgment 110 of Figure 11, the data area signal d
(Fig. 11E) is determined between high level H and low level L, and when the data area signal becomes low level, processing 11
1, the CPU (4) to RAM (61
A command to send data 1 is issued, and data 1 is sent to the data bus (8). At the same time, the address decoder (to) empty signal j80H shown in FIG. 10 is output.
Data 1 on the data bus (8) is loaded into the serial converter.

In addition, the signal 80H sets the frizz frozzo wire, opens the dart (c), and writes data 1. The writing period D1 of data 1 is determined by the following judgment 112.
This continues until it is detected that the data area signal becomes low level.

When the determination 112 becomes Y (yes), the next data 2 write period D2 begins, and in the process 113, data 2 is sent out, loaded, and the flip frozzo wire is set in the same manner as described above. When the writing of the necessary data is completed, in process 115, the address decoder (to) outputs the signal 8-.
1H is output, the frizzo flop wire is reset, and writing of one field is completed. Next, the process returns to decision J1 and writing of the next field is executed.

Next, the reproduction control of the videotape (1) shown in FIG. 1 will be explained.

As mentioned above, programs R, P2, etc., which control the playback of the VTR (2+) are written on the videotape (1). When the playback of the VTR is started, the first program Gram PI is read and microcomputer (3)
The program for reading this first zorogram is stored in the I10 interface circuit (3) of the microcomputer (3) shown in FIG.
13) is written in the ROM provided on the expansion board. The ROM that stores this fixed program is called an initial loader.

FIG. 14 is a flowchart showing the initial loader program. First, when the control system is started, message information is outputted to, for example, the printing device (10) in FIG. 2 in step 121. Next, a cueing routine L1 is entered, and in step 122, the current address of the playback track is read. The read address is compared at decision 126 to the destination address to which the first program was written.

The address of this first f program is the same for every tape.

If the comparison result with the target address is N (no),
In process 124, the VTR is rewound or fast-forwarded, and the cueing routine L1 is continued.

When the result of the judgment 126 is Y, the cueing routine ends, and the first program P is read and RA is performed in a process 125.
Writing to M (61 is performed.

FIG. 15 is a block circuit diagram of a data reading circuit included in the I10 interface circuit of the microcomputer, and FIG. 16 is a time chart for explaining the program interrupt operation for reading data in FIG. The figure is a flowchart of this interrupt operation.

As shown in FIG. 15, it is equipped with a controlled VTR (21 beam mode control (remote control) terminal G7),
By supplying the control signal RC of the remote control control output line (to) of the microcomputer (3) via the remote control control circuit O1, fast forwarding, rewinding, playback, etc.
Remote control control such as high-speed playback (picture search) is performed.

The playback output e of the VTR (2) is connected to the video switching circuit (41
It is sent to the monitor (4υ) via the video switching circuit (
40 (r), a video signal Cv formed by a computer is supplied from a terminal (421) and V T R (2
), the switching circuit is controlled so that when there is no reproduced video output e, message 1, question, etc. are displayed based on the video signal C2.

In order for the microcomputer (3) to read data (address data, program data) from the playback output e of the VTR (21) and to store the necessary data, first the microcomputer (3) is required to read the data. An interrupt request (Interrazoto request) is made.This interrupt request causes the microcomputer (3) to
The operating mode is switched from the main program to a data reading program routine. Interrupt request is reproduced signal e
Vertical synchronization signal is applied to V-8YNC store. That is, the reproduced signal of the VTR (2) is sent to the synchronization separation circuit (43I), and the vertical synchronization signal V-8YNC (
Figure 16A) is the interlat control circuit (4
4) − is given. This interlat control circuit (4) is composed of, for example, an RS Frizzo Frozzo, and when V-8YNC is supplied to its set input, a low level interrupt request signal I is output at its Q output.
RREQ (FIG. 16B) is formed. This signal is applied to the terminal (4!19) of the microcomputer (3), and an interrupt request is made to the microcomputer (3).

As shown in the flowchart of FIG. 17, as described above,
First, when the arrival of the vertical synchronization signal V-8YNC is detected in judgment 130, an interrupt request is set in process 131. As a result, the computer (3) executes the interrupt routine program in step 162 and reads necessary data. Interrupt cancellation is performed by the interrupt routine program. That is, the program is created so that the interrupt request is reset in step 136 when the necessary data has been fetched, and the interrupt request is thereby canceled. To cancel an interrupt request, use the terminal (4f) of the microcomputer (3) shown in Figure 15.
The interrupt request reset signal NIR, R8T is sent from D to the interlat control circuit (44), the flip-flops forming this control circuit are reset, and the interrupt request signal returns to high level as shown in FIG. 16B. Then, it is done by and.・When the interrupt request signal becomes high level, the interrupt disabled state is canceled and
As soon as the next interrupt is enabled, program execution moves to the main program (return by instruction 164 in FIG. 17).

In a normal video playback period, as shown in FIGS. 16A and 16B, address data ADR immediately after V-8YNC is read in interrupt routine IR(a), and then the main program M is returned. In the program recording section on the tape, after an interrupt request is made with the vertical synchronization signal, the 16th
The interrupt routine IR(c) shown in FIG.

Next, FIG. 18 is a time chart illustrating the operation of the data reading circuit of FIG. 15 when reading data, and FIG. 19 is a flow chart illustrating this operation.

When reading data, the reproduction signal e(
Fig. 18A)
Sliced at level U in diagram A, F in diagram 18
M data f (address data or program data)
is extracted. The pedestal clamp is connected to the horizontal synchronization signal H-8YNC (first
This is based on the cranzonoculus g obtained by delaying the video signal (FIG. 8B) to the back porch of the video signal as shown in FIG. 18C using a delay circuit (481).

The output f of the flange/slicer (47) is sent to the FM demodulator (
41, and the demodulated data h ("1'" shown in FIG. 18E) is sent to
is returned to high level and 0'' is returned to low level).Furthermore, F
As mentioned above, the M data f is a transmission signal having a self-clock, and the FM demodulator (41 The 8-bit shift clock i shown in FIG. The data is sequentially shifted into an 8-bit shift register and converted into parallel data.The 8 pit numbers and parallel data j output from the converter are applied to each line of the data bus (8) of the microcomputer (3).

The data given to the data bus (8) from the serial converter (5) shown in Fig. 15 is taken into the RAM (61) of the microcomputer (3).The timing of data taking is shown in Fig. 18. It is synchronized with the output of a bit counter 61) that counts the shift clock i for 8 bits of F. Generally, when - serial or parallel conversion operations are completed, that is, 8 bits of serial data are In order to load the converted data into the RAM each time it is sent to the serial-to-parallel converter, the bit counter []) is configured to generate a timing output every time the shift clock is counted by 8v. be done. However, in the control system of this embodiment, data transmission is performed using a self-clock method as described above, so if there is a dropout of a few bits in the data, 8 bits of data will not be aligned within one horizontal section. Data acquisition may be difficult.

Therefore, in this embodiment, the bit counter 6]) is set to 8 bits, and a 6-bit signal k shown in FIG. 18G that rises at the 6th bit and falls at the 8th bit is obtained from its output. This 6-bit signal is applied to the data bus (8) via the tri-state passer 6. This buffer 6 is brought into conduction by the read command signal RD output to the terminal - of the microcomputer (3), and the output is normally open.

In the computer (3), data is read using the upper≧6 bit signal k as a flag. That is, the 19th
As shown in the flowchart of the figure, the judgment 140f, ! S
It is detected that the S pit number k changes from a low level L to a high level H, and after a delay process of about 6.75 μs in a process 141, data 1 within one horizontal section is read in a process 142. The 6.75 μS delay is provided in anticipation of the arrival of the 8th bit of data. According to this reading method, even if there are 2 bits dropped out in one horizontal section, if at least 6 bits of data arrive, a reading flag is always formed and data is taken in. Of course, this data is incorrect.

As described above, since the same data is written in three adjacent tracks, if it is determined that the data is incorrect, the correct data can be read from the next track or the next track.

The bit counter 1l)D and the serial to parallel converter 6I are cleared by the delayed horizontal synchronizing signal g (Fig. 18C) output from the delay circuit (48) when reading of data within one horizontal interval is completed. Clearing by the delay signal g secures the data read section R shown in FIG. The data is loaded into RAM.

When data reading for one horizontal section is completed, judgment 143, processing 144, 145, etc. in the flowchart of FIG. 19 are completed.
The data of the next horizontal section is read as follows. The data read flag may be set at the 5th or 7th bit of the reproduced data.

The data read in this manner is stored in a buffer memory within the microcomputer (3), subjected to an error check using a CRC code, and written to the RAM (6). Error checking by CRC is shown in Figures 8A and 8B.
As shown in the figure, the 6 tape is susceptible to defects and has triple writing.
The majority vote system, which identifies good data by matching two of three identical data from a book track, loses its rationale in the presence of read loss (data dropout). In particular, if one 128-byte data block of the six-fold write is correctly read, but there are errors in both of the other two blocks, the majority vote will result in the data being unreadable.

Therefore, in this embodiment, the error check by CRC shown in FIGS. 20A to 20C is used in combination with majority logic to reduce reading errors.

In other words, the first and second tracks of the triple writing are checked for errors using CRC, and if both of these checks fail to detect errors, the read data of the third track and the previous two 20A is a flowchart for reading data in the first track. First, in process 150, 128-byte data in one field is detected. is read and written to the notother memory.Next, error detection is performed using the CRC code added to one data in step 151.If an error is detected, an OK flag is set in step 152, and if there is no If so, please reset the OK flag in process 153.

For the second track, as shown in FIG. 20B, the OK flag is first determined in judgment 160, and if it is set, the good data of the first track in the buffer memory is stored in the memory (RAM) in process 161. ) Transfer to +61. If the OK flag is reset (2), the same thing as the data reading and checking in the first track is performed on the data in the second track. That is, in process 162, 12
Reads 8 bytes of data and writes it to memory, then performs error detection using a CRC code in decision 163;
Depending on the detection result, the OK flag is set (process 164) or reset (process 165).

Next, in the sixth track, judgment 1 is made as shown in Fig. 20C.
The OK flag is determined in step 70, and if it is set, the data of the second track written to the memory in step 162 of FIG. 20B becomes valid data. If the OK flag is reset, operation 171 reads one byte of data, and decision 172 reads 6 the data consisting of this data and the corresponding data of the first track in the buffer memory and the corresponding data of the second track in memory. Detection of a match between the two pieces of data is performed, and if a match is detected, the match data is written into memory in step 176. The work of extracting good data based on this majority vote is performed for 128 bytes, and when all is completed, the reading of one program segment is completed by detecting the end in judgment 174. If judgment 17
If no match is detected in step 2, an error is displayed in step 175, the VTR is rewound, and the program proceeds to read another block on the tape in which the same program has been written.

When performing majority voting as described above, if a 1-byte read drop occurs while reading each 128" byte of data, the data arrangement will be shifted thereafter, making it difficult to take majority voting. This embodiment Now, when reading data, as mentioned above, the output of bit counter CD 6 in FIG.
A flag is set at the rising edge of the bit signal, and one byte of data within one horizontal section is taken in. Therefore, when there are many bit drops, the flag by the 76-bit signal may no longer be raised, and one byte of data may be lost. Since the memory area corresponding to this missing data is filled with the next data, the data arrangement gradually shifts each time missing data occurs. For example, data D1
, D2, Ds array, 6-fold write torano is also 0
The following Table 1 situation can occur for a read data of 0.01.02.

Table 1 Track data 00 Dt, I)t, Dso 1
Dl, Ds,? o2D2, Ds,? In the above table, reading of track 00 is performed normally, data D2 is missing in track 01, and data D1 is missing in track 02. Therefore, if the majority logic is applied to the read data of the six tracks in Table 1, it will become difficult to execute, or there will be a problem in that incorrect data is regarded as correct data.

For this reason, in this embodiment, data acquisition by software, which sets a flag using the 6-bit signal, is used in combination with data acquisition by software. The loop program for checking flags for data reading in decisions 140, 143, . . . in FIG. 19 is as follows.

LD C,7E OP OP OP 0P IN A, (read) First, set 7E (hexadecimal number) in the C register,
Next, a 6-bit signal k (flag) is taken into the MSB of the A register (INA,). This MSB is a signal bit, and if it is 1 (negative), it means that a flag has been set, and 1 byte data of 1 water section passes through serial roots and parallel converter 5 [) in Figure 15. Computer (3
).

Next, increment (INC) C increments the contents of the C register by +1, and further, or (OR) C, the OR of the MSB of the A register and the C register is placed in the A register. As a result, if the MSB of the A register is 0 (positive), a jump is made to procedure number D128, and the 6-bit signal k (flag) is detected again. When the flag is set, the MSB of the A register becomes 1'', the flag is removed from the detection loop, and the data is read into the A register (IN, A) after a four-time N0P (no operation) delay. The delay due to NOP corresponds to the delay processing in processes 141, 144, etc. in Fig. 19, and during this time, the microcomputer detects the arrival of the 8th bit from □ when the 6-bit signal flag is set. Waiting. When data acquisition, checking, and transfer to memory are completed, the preset value is placed in the C register again.

If a bit dropout occurs and the flag is not raised by detecting a 6-bit signal, the flag detection loop continues to operate, and each time this loop is executed, the
The contents of the register increase by +1, so for example, C
The MSB of the register becomes 1" due to carry. Then, in the next ORC, "1" (negative sign) is entered in the MSB of the A register, so the detection loop is exited and data is taken in. Therefore, even if bit dropout occurs and a 6-bit signal is not formed, the data will be captured after a certain period of time, so there will be no data loss, and therefore the majority logic can be used effectively. can. That is, as shown in Table 2 below, even if there is erroneous data x, the data order does not shift, so good data can be extracted by majority vote.

Table 2 T, rack data [10'D+ Dt Ds ol D+ × Da02
x Dt D3 majority vote D, ″ D,
D.

The number of loops to be set in the C register is determined as follows. In other words, if the execution time of one reading flag detection loop is, for example, 7.25 μsec, it is 66.5 μsec (
Loop count) x 7.25 μs + (other execution time) x 66
．． After a time of 5 μs + 7.25 μs, that is, 63.5 μs (I H) + α, data is captured even if there is no flag. Then, in the next data reading, if the flag is set normally, the data will be taken in before the time of 63.5 μS+α has elapsed. At this time 6
The timing of the software that performs the above-mentioned time measurement is synchronously combined (resynchronized) with the data acquisition timing using the bit signal k as a flag. Note that "6 other execution time" refers to error checking performed within the microcomputer,
The time required for data transfer, etc. (other execution time) + (287, 25μ8) < 63.
It is necessary to satisfy 5 μs. That is, 1) When a drop occurs, data is captured after a time of 65.5 μs + α, so in order to jump to a loop that detects the capture flag within 63.5 μB in the next reading operation and jump by 3Δ, 66. It is necessary to estimate the "other execution time" to be shorter than the time obtained by subtracting twice the loop execution time from 5 μB. The other execution time may be, for example, about 68 μS. Note that there is a need to make the execution time of the flag detection loop (processing 140 in FIG. 19) shorter than the allowable time for reading data.

(The following margins are continued on the next page.) As described above, the present invention forms a clock pulse synchronized with the bits constituting the program or data of the reproduction output of the video signal reproduction device, and It is counted for each scanning section, and each time the counted value reaches a predetermined number, a data read command is given to the computer by 4, and if there is no read command before the elapse of a predetermined time since the previous data read, this time elapsed. Since the data is loaded based on the detection of 1, data reading is always performed even if there is a bit dropout in the reproduced output data.

Therefore, data loss (missing) does not occur, processing of read data (majority extraction of multiple write data, error 1 correction), etc. can be performed without any problems, and data with extremely high reliability of 9 can be obtained.

[Brief explanation of drawings]

FIG. 1 is a plan view of a tape showing information recorded on a video tape used in the VTR control system of the present invention, and FIG. 2 is a block diagram of the entire VTR control system.
The figure is a plan view of the tape showing the track pattern on the videotape, and Figure 4 is a waveform diagram showing the format of digital signals such as bit addresses and programs.
The figure is a line diagram showing the data writing format for each field, Figure 6 is a diagram showing the track of the program writing area on the tape, Figure 7 is a plan view of the program block tape, and Figure 8A is a diagram showing the write format of data for each field. Figures 4 and 8B are partial plan views of the tapes with damage to the data recording portion, respectively, and Figure 9 is the glue 4bchi'r- for questioning the shifted recording of the data recording part.
), FIG. 10 is a block circuit diagram of the data write circuit included in the I10 interface circuit of the microcomputer, and FIG. 11 is its operating waveform.
The figure is a flowchart showing the control program of the microcomputer during data writing, Figure 14 is a flowchart showing the initial loader program of the microcomputer), and the total 15 figures are the microphone o *.
7. t' : L-ta(DI/0 iy 51-
7 x - Included data, block circuit diagram of the evening reading increase circuit, Figure 16 is a time chart to explain the program-1 read operation of the circuit in Figure 15 for reading data, 17th Fg is this interrupt 70 to explain the operation
-Charts, Figure 18 is a time chart illustrating the data reading operation of the circuit in Figure 15, Figure 19 is a flowchart explaining the data reading operation, Figures 20A to 20
0g is a flowchart of checking work for increasing data reading in each microcomputer. In addition, depending on the symbols used in the drawings, (11----
−−−−−・・・・・・Video tape (2)−・・・
・・・・・・・・・−v'r'a13+・・・・・・−・・
・・・・・・Microcomputer (41・・・・・・
・・・・・・・・・0PU(5)－・・・・・・・・・
...ROM (61...--R
AM4・・・・・・・・・・・・FM demodulator 6υ
・・・・・・・・・・・・・・・Pit counter. Representative: Owner: Osamu Matsumura

Claims (1)

[Claims] In an information reading system that reads programs or data handled by a computer from a video signal reproducer using a tape-like recording medium, bits constituting the program or data reproduced by the Eirin signal reproducer described above. means for forming a clock pulse synchronized with the clock pulse, a counting means for counting the clock pulse every two horizontal scanning sections and giving a data reading command to the computer every time the counted value reaches a predetermined number; and a means for detecting the elapse of a predetermined time from the previous data read, and when the data read command is not received before the elapse of the predetermined time, the output of the detecting means is activated. Information vtMIL resystem that incorporates τ data.