JPS5846788B2 - Kiokusouchi - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a storage device including a cyclic shift register formed of a shift register storage element such as a magnetic bubble element or a semiconductor element.

In particular, the present invention relates to a storage device that operates by detecting the address of information existing at a storage location in a circular shift register during a read or write operation.

Conventional storage devices using majors made of magnetic bubble elements and chips with a minor loop type chip configuration utilize the reference information stored in the minor loop to detect the accumulation existing at the storage location of the minor loop. A counter was initially set to detect the address of the information.

However, in such a storage device, the time required to read the reference information and initialize the counter when the power is turned on is proportional to the number of times the minor loop information is repeatedly read.

When selectively moving information in each of the magnetic bubble element modules in this storage device, it is necessary to initialize the counter provided for each module. The disadvantage is that the time required increases and cannot be ignored in terms of operation.

Furthermore, since only one piece of reference information exists in the minor loop, once the reference information is lost when the operation of the storage device is abnormal, there is a drawback that subsequent operation becomes impossible.

An object of the present invention is to shorten the initial setting time of a storage device including a circular shift register and improve the reliability of the storage device.

According to the present invention, in a storage device including a plurality of cyclic shift registers, a first cyclic shift register containing address information in a plurality of storage locations at predetermined intervals, and mark information for identifying the information are provided. a second circular shift register including a second circular shift register; an address counter that is initialized based on the address information and the mark information and whose contents change as information in the plurality of circular shift registers moves; According to the present invention, there is provided a storage device comprising means for accessing information in the plurality of circular shift registers based on the address information stored in the address counter and the contents of the address counter.

There are no restrictions on the type of memory element used in the memory device of the present invention.

However, as an embodiment of the present invention, a storage device using a magnetic bubble element will be shown.

Next, the present invention will be explained with reference to the drawings.

FIG. 1 shows a major minor loop type memory chip configuration of a magnetic bubble element that has been proposed in the past.

The original form of this chip configuration was published in the magazine "Scientific American J (5ci)" published in June 1971.
entific American), Volume 224,
No. 6, p. 90.

The solid line with an arrow represents the path of movement of the bubble magnetic domain.

Information is stored in minor loops 1-6 as a plurality of circular shift registers.

Minor loops 1-6 are transfer gates 11-1
6 to a major loop 17 in which an input/output section is arranged.

The input/output section includes magnetic domain detectors 18-1 for detecting information transferred to the major loop 17. A magnetic domain input device 18-2 for inserting information into the major loop 17 according to write information and a magnetic domain eraser 18-3 for selectively erasing magnetic domains of the major loop 17 are included.

The details of the operation are similar to those shown in the above-mentioned document and will therefore be omitted.

Note that the portion having the chip configuration shown in FIG. 1 is the smallest unit that can be functionally independent, so it will be referred to as a chip unit.

Note that a chip unit is simply referred to as a chip unless there is a risk of confusion.

FIG. 2 is a block diagram of a storage device according to the present invention using a magnetic bubble element.

An address signal line 2 is connected between the storage device 20 and the external circuit.
1-L person data line 21-2, output data line 21-3,
and a control signal line 21-4.

A large number of magnetic bubble element chips having the chip configuration shown in FIG. 1 are arranged in the storage main body 22.

Direct peripheral circuits include a bias magnetic field device 23 for making bubble magnetic domains exist stably, a rotating magnetic field device 24 for moving bubble magnetic domains, and a magnetic domain detector 18.
-1 reading circuit connected to magnetic domain input device 18-2
a write circuit connected to the magnetic domain eraser 18-3, an erase circuit connected to the magnetic domain eraser 18-3, and a transfer gate 11-1.
A circuit 25 including a gate drive circuit connected to 6
is located.

Furthermore, a control circuit 2 that directly controls the operation of these peripheral circuits
There are 6.

The minor loop of the chip in the memory main body 22 includes a minor loop that stores information to be stored, and control information that is used to detect the address of the stored information that exists at a storage location within the minor loop. There is a minor loop that remembers.

Output data from the circuit 25 is input to a control circuit 26 so that this control information can be used.

Next, the storage state of the control information stored in the minor loop in the magnetic bubble element chip will be shown using FIGS. 3 to 5.

If a black circle is written in the memory position, there is a magnetic domain there.
If a white circle is filled in, there is no magnetic domain, and if neither a black circle nor a white circle is filled in, it is assumed that there is no magnetic domain.

Note that the chip configuration of the major minor loop method in the following figures is more simplified than that in FIG. 1.

It is assumed that the number of bits of the major loop and the minor loop are 35 bits and 36 pits, respectively.

FIG. 3 shows a state in which the minor loop storing control information in the chip in the storage main body 22 is closed at a certain time.

Storage location PO, P8 of minor loop 321. P16,
And mark information 1 represented by magnetic domains only on P24
11'' is present.

Address information for identifying these mark information Jll exists in corresponding storage locations of minor loops 322 and 32-3.

That is, the address information II o of the storage position PO of the minor loop 323 and the minor loop 32-2 is set to the mark information of the storage position PO of the minor loop 32-1.
o°' exists, and the memory location P of the minor loop 32-1
Address information +01n of the storage position P8 of the minor loop 32-3 and the minor loop 32-2 exists for the mark information of 8, and the address information +01n of the storage position P16 of the minor loop 32-1 exists. The address information 1110'' of the storage location P16 of the loop 323 and the minor loop 32-2 exists, and the minor loop 32
-3 and address information 11111' of storage location P24 of minor loop 32-2 exist.

Mark information of these minor loops 32-1, minor loops 32-2 and minor loops 32-3
The address information constitutes control information.

FIG. 4 shows the state of the minor loop storing control information in a chip within the storage main body 22 at a certain time.

In the minor loop 421, storage positions PO, P8. P16
, and mark information “1” represented by magnetic domains only on P24.
” exists.

Address information for identifying these mark information +111 exists in the minor loop 42-2.

That is, for the mark information at the storage position PO of the minor loop 42-1, the storage position P1 of the minor loop 42-2 is
and PO information “00” exists, minor loop 4
Information 1011 of storage positions P9 and P8 of minor loop 42-2 for mark information of storage position P8 of 2-1
exists, and information 111011 exists in storage position P17 and PI3 of minor loop 42-2 for mark information in storage position P16 of minor loop 42-1, and information 111011 exists in storage position P24 of minor loop 42-1. Storage positions P25 and P of the minor loop 42-2 for mark information
There are 24 pieces of information 1111'.

As explained above, the minor loops 42-1 and 42
-2 information constitutes control information.

FIG. 5 shows a state in which the minor loop storing control information in the chip in the storage main body 22 is closed at a certain time.

Here, the control information stored in the minor loops 32-1 to 32-3 in FIG. 3 is distributed to different chip units.

That is, the control information stored in minor loops 32-1, 32-2 and 32-3 is stored in minor loop 52 belonging to major loop 51, minor loop 54 belonging to major loop 53, and It is stored in a minor loop 56 belonging to the major loop 55.

In FIGS. 3 to 5, only minor loops storing control information are shown, and minor loops for stored information existing above these minor loops are omitted.

The numbering of accumulated information stored in the minor loop is done based on control information.

For example, in the states shown in FIGS. 3 to 5, the number of accumulated information in the storage position PO of the minor loop is set to 0.

In other words, the number of accumulated information located at the same storage location relative to the storage location where the mark information corresponding to the address information having the value of 1100L1 exists is set to 0.

Then, the storage position pLp2. is located clockwise from the storage position where the accumulated information with number O exists.・・・・・・P35
The stored information numbers are sequentially 1.2, ..., 35'
becomes.

Note that the number of accumulated information located at a storage location relatively a fixed storage location away from the storage location where mark information corresponding to address information having the value of @ o o W exists may be set to 0.

Typically, the information specified by the address signal consists of 2 bits of information located in adjacent storage locations in each minor loop.

In this case, the accumulated information of numbers O and 1 is at address 0.
The information is generally number 2 (n-1) and number (2n
The accumulated information of -1) becomes the information of address n.

Since it is assumed that information is transferred uniformly within one magnetic bubble element module, the number of chips or chip groups containing control information as shown in Figures 3 to 5 is small within the module. It is sufficient that one of each exists.

In FIG. 3, three minor loops for control information are required, whereas in FIG. 4, two minor loops for control information are required.

If 2 bits of information are transferred in one transfer operation between the minor loop and the major loop, the control information stored as shown in Figure 3 is transferred to the major loop in one transfer operation. In contrast, the control information stored as shown in FIG. 4 is transferred to the major loop in one or two transfer operations.

The stored control information as shown in Fig. 5 is transferred to the major loop in one transfer operation, which is the same as in Fig. 3, but from the magnetic domain detector of each chip unit in parallel. This differs from FIG. 3 in that it needs to be read exactly.

When control information is stored as shown in FIG. 5, the bubble memory device configuration requires that at least the chip units storing the control information in the module be in the read state at the same time. Give constraints.

However, since the control information is read in parallel, it is convenient for configuring a control circuit.

FIG. 6 shows a portion of the control circuit 26 and a portion of the circuit 25 of the bubble memory shown in FIG. 2, which operate based on control information stored in the magnetic bubble element chip.

In the bubble memory, control information is stored as shown in Figure 5, and a chip configuration is adopted in which the major loop is 35 bits and the minor loop is 36 bits as shown in Figure 5. It is assumed that there is

It is also assumed that the method of determining the stored information number based on the control information in the minor loop and the correspondence between the stored information number and address are as described above.

Amplifying width shaping circuit 61 within circuit 25. Width shaping circuit 63
, and the respective input terminals of the width shaping circuit 65,
A magnetic domain detector mounted on the major loop 51, a magnetic domain detector mounted on the major loop 53, and a magnetic domain detector mounted on the major loop 55 are connected.

It is assumed that the magnetic domain detector exists at the magnetic domain position PO of the major loop.

Since the number of bits in the minor loop is 36 bits, counter 60 is a 36-bit binary counter.

An input terminal 60 of the counter 60 receives a count up pulse that increments the contents of the counter by one each time the information moves one storage position within the minor loop.

Since the counter 60 is initialized as described in detail later, based on the correspondence between the agreed storage information number and the address, the upper five digits of the contents of the counter 60 are the information that exists in the storage location PO of the minor loop. It shows the address of.

Therefore, the output of the top five digits of the contents of the counter 60,
More specifically, if the address signal and the in-chip address signal are applied to the input of the 5-bit comparator 66,
The output of the comparator 66 allows access to the stored information.

Specifically, a gate current is supplied from a gate drive circuit for the transfer gate based on the output of the comparator, and the stored information at the designated address is transferred from the minor loop to the major loop.

The operation of the counter 60, which is initialized based on control information in the minor loop of the chip, will be described.

Here, the unit of information transfer between the minor loop and the major loop is set to 2 bits, and current is supplied to the transfer gate of each chip unit to transfer the information at the storage locations PO and Pl of the minor loop to the main units. shall be forwarded to the loop.

Since it is assumed that the magnetic domain detector exists at the storage position PO of the minor loop, the storage position PO (P
The period of the rotating magnetic field until the information of 1) reaches the magnetic domain detector is uniquely determined to be 4 (5) periods.

When the 2-bit information to be transferred exists in the storage locations PO and PI of the minor loop, a signal that becomes II I If is applied from the terminal 64 at the 2-bit transfer time of 4 cycles and 5 cycles after the 2-bit information to be transferred exists in the storage locations PO and PI of the minor loop. Ru.

Assume that the reading operation of two pits from the minor loop of each chip is repeated in sequence, and a state as shown in FIG. 5 is obtained.

Next, when 2 bits of information are transferred from the storage locations PO and Pl of the minor loop to the major loop, the information will be transferred to the storage location PO of the minor loop 52 after 4 cycles from the state shown in FIG.
Since the magnetic domain located at 2 reaches the storage location PO of the major loop 51, the output of the amplifying and shaping circuit 61 becomes ``1''1.

At this time, since the signal from the terminal 64 is also 111'', the II I If output of the AND gate 68 is applied to the LOAD terminal of the counter 60.

At this time, the outputs of the amplifying width shaping circuit 63 and the amplifying width shaping circuit 65 contain the information "oo" that was in the storage position PO of the minor loop 54 and the minor loop 56 in the state shown in FIG.
occurs.

Fixed signals OIl, O'', and 'lI'' are input to the data inputs of the first to third stages of the counter 60, respectively, and amplified signals are input to the data inputs of the fourth and fifth stages, respectively. Output signals of shaping circuits 63 and 65 I+ 01, It □
It is input, and a fixed signal of 0'' is input to the data input of the sixth stage.

Therefore, if 1 is applied to the LOAD terminal of the counter 60.
When the 1 signal is applied, the counter 60 is initialized to 000100.

Accumulated information with number 4 exists in the storage position PO of the minor loop that stores accumulated information at this time.

Since the contents of the counter 60 are incremented by 1 each time the information power of the minor loop moves by 1 bit, it indicates the number of stored information existing in the storage location PO of the minor loop.

Furthermore, the upper five digits of the contents of the counter indicate the address of the stored information existing at the storage location PO.

In FIG. 5, the control information existing in the storage position PO is changed from the state in which the control information exists in the storage position P1 to the storage position PO.
Even if 2-bit information is transferred from Pl to the major loop, the signal applied from terminal 64 will still be 111n after 5 cycles, so counter 60 will be o
Set to ooiooo.

In FIG. 5, when control information existing at storage location P8 is present at storage location PO or Pl, and 2-bit information is transferred from storage locations PO and Pl to the major loop, After 4 cycles or 5 cycles, the output of the width shaping circuit 63 becomes 1'', and the width shaping circuit 6
The output of 5 is "0".

As a result, the contents of the counter 60 are initialized to 001100.

This value corresponds to the number of stored information existing in the storage location PO of the minor loop at this time.

Even if the counter 60 is initialized using other control information, the contents of the counter 60 and the number of accumulated information existing in the storage location POO of the minor loop at this time match.

If there is a chip unit in the magnetic bubble element module that does not store control information and operates simultaneously with a chip unit that stores control information, the circuit 25
The width shaping circuits 61, 63 and 65 shown in FIG.
There are other width-enhancing shaping circuits.

If the bubble memory consists of a plurality of modules and information is not transferred in all the modules at the same time, a control circuit as shown in FIG. 6 is required for each module.

Note that if information moves in the bubble memory in both directions, counter 60 becomes an up/down counter.

The storage device of the present invention has been described above using a magnetic bubble element chip having a specific chip configuration.

Since four sets of control information are stored in the minor loop as shown in FIGS. 3 to 5, the time required for initializing the storage device is reduced to one quarter of that of the conventional method.

Furthermore, even if some of the four sets of control information are lost for some reason, the counters in the storage device can be initialized with the remaining sets.

In the embodiment of the present invention, a specific chip configuration is used for the magnetic bubble element chip, but if the chip configuration changes, the control circuit and the signals given to the control circuit must also be changed accordingly. should be clear from the above explanation.

[Brief explanation of the drawing]

FIG. 1 shows a major minor loop type memory chip configuration of a magnetic bubble element that has been proposed in the past. FIG. 2 is a block diagram of a bubble memory according to the present invention. Figures 3 to 5 show a state in which the control information stored in the minor loop as a circular shift register in the chip used in the bubble memory according to the present invention is in a down state at a certain time. . FIG. 6 shows a control circuit for the bubble memory shown in FIG. In the figure, 32-1, 421, 52 is a minor loop that stores mark information, 32-2, 32-3,
42-2, 54, and 56 are minor loops that store address information; 60 is a counter that is initialized based on control information and whose contents change as the information in the minor loop moves; and 69 is an address signal. The input terminal 66 is a comparator.

Claims (1)

[Claims] 1 In a storage device including a plurality of cyclic shift registers, a first cyclic shift register includes address information in a plurality of storage locations at predetermined intervals, and a second cyclic shift register includes mark information for identifying the address information. a circular shift register, an address counter that is initialized based on the address information and the mark information and whose contents change as information in the plurality of circular shift registers moves, and address information given from the outside. and means for accessing information in the plurality of circular shift registers based on the contents of the address counter.