JPS5811711B2 - Storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a storage device using a storage element that performs an access operation by moving information, such as a magnetic domain storage element that uses a single domain wall domain represented by a cylindrical magnetic domain as information. There is a scholar.

Here, a magnetic domain storage device using a magnetic bubble element that uses the presence or absence of a cylindrical magnetic domain as information as a storage element will be described as an example.

Chip configurations of magnetic bubble elements used in storage devices include a decoder type chip configuration, which is a type of spatial selection type, and a major minor loop type chip configuration, which is a type of time selection type.

Here, we will discuss a magnetic bubble element with a major minor loop (M/m) chip configuration.

In addition, the magnetic bubble element with M/m type chip configuration is 19
This is proposed in the magazine Scientific American, Vol. 224, No. 6, pp. 78-90 (Reference 1), published in June 1971, especially on page 90.

One major loop in which an input/output section exists and a plurality of minor loops connected thereto are called a chip unit of a magnetic bubble element.

Given the bit transfer rate of the magnetic bubble element, the storage capacity of the storage device using the magnetic bubble element, the access time, the data transfer rate, etc., the configuration of the chip unit,
That is, the number of bits of the minor loop and the number of minor loops are determined, and furthermore, the number of chip units is determined.

Generally, when information is accessed in a storage device, this information is contained in a portion of multiple chip units.

Therefore, if a permalloy pattern is used as a means to move information represented by the presence or absence of magnetic domains within a magnetic bubble element, it is only necessary to apply an in-plane rotating magnetic field to the chip unit containing the information to be accessed. Become.

Since magnetic bubble elements can stop information for an infinite amount of time, storage devices using magnetic bubble elements are convenient for such operations.

On the other hand, the power consumption for generating the rotating magnetic field is proportional to the space in which the rotating magnetic field is to be generated, so from this point of view as well, it is desirable to apply the rotating magnetic field only to the chip unit containing the information to be accessed.

However, when performing such an operation, in order to identify the magnetic domain position where stored information exists, it is necessary to prepare an address control unit including a counter for each of the multiple chip units to which a rotating magnetic field is simultaneously applied. Must.

Depending on the configuration of the storage device, the number of address control units including counters may be considerable.

Moreover, since the contents of these counters must be saved even if there is a power outage, countermeasures against power outages are required.

In a storage device using a conventional magnetic bubble element, it is preferable to apply a rotating magnetic field only to the chip unit containing the L information that must be accessed from the viewpoint of power consumption, but the control device including the counter for identifying the information becomes complicated. This has hindered the reduction in prices of storage devices.

SUMMARY OF THE INVENTION An object of the present invention is to simplify the address control section of a storage device that selectively moves information within a storage element, thereby reducing the cost of the control device.

FIG. 1 is an example of a chip unit of a magnetic bubble element used in the storage device of the present invention.

The thick solid line represents the movement path of the magnetic domains.

Information is stored in the plurality of liner loops 111-116.

Liner loops 111-116 are memory gates 141-1
It is connected via 46 to a major loop 117 in which an input/output section is arranged.

The input section is composed of a magnetic domain generator 131 that generates a magnetic domain every cycle of the rotating magnetic field, a magnetic domain eraser 132, and a write gate 147, and the output section is composed of a magnetic domain eraser 133 and an erase gate 14.
8 and a magnetic domain detector 134.

In a storage device using such a chip unit,
Data specified by address information is stored in corresponding magnetic domain positions of a plurality of liner loops within a specific chip unit.

Note that data may be stored across multiple chip units.

FIG. 2 shows how information is transferred in a storage device according to the present invention using a magnetic bubble element.

In the figure, in order to selectively move information within the storage element,
When a rotating magnetic field is selectively applied to a chip unit, a part of the selected chip unit in the memory section to which the rotating magnetic field is applied, that is, a part of the major loop 200 and one liner loop 201 are simplified and shown by dotted lines. A memory gate 202 is shown.

The liner loop 201 has 256 bits, and the major loop 200 has 255° bits.

It is assumed that two bits of information belonging to an arbitrary address within a chip unit are stored in each liner loop.

Therefore, the number of addresses in the chip unit is 127 counting from O.

The magnetic domain positions of the major loop 200 are marked with P1 to P255, and the magnetic domain positions of the liner loop 201 are marked P1 to P2.
Marked with 56.

In the chip unit, before operation, as shown in FIG.
It exists in 5.

Also, the information of address “1” is the magnetic domain position P253 and P2
Located in S5, address “2”, address “3”, etc.
The information exists sequentially at magnetic domain positions in the counterclockwise direction of the liner loop 201.

Next, the movement of information within the storage device will be explained using an example of the operation of reading information at address "3".

In the state shown in FIG. 2a, if a rotating magnetic field is applied to the selected memory section including this chip unit to selectively move information, after 6 cycles the address "3'' information reaches the magnetic domain positions P255 and P2S5 of the liner loop 201.

Thereafter, when the memory gate 202 is opened for two rotational magnetic field periods, the information at address "3" is transferred to the major loop.

By moving through the measurer loop 200, this information is converted into read information by a detector in the measurer loop.

After 256 cycles from the state shown in FIG. 2, the information at address "3" reaches the magnetic domain positions P1 and P2S5 of the major loop 200, as shown in FIG. 2C.

At this time, the empty information that contained the information for address "3'" is
The magnetic domain positions P255 and P2S5 of the liner loop 201 have been reached.

Thereafter, when the memory section 202 is opened for two cycles, the information at address "3" is transferred to the liner loop 201.

After 512 cycles from the state shown in FIG.
Since P2S5 is reached, the application of the rotating magnetic field to the chip unit is stopped to stop the movement of information at this point.

In this way, the address “
The movement can be stopped at P2S5 and P2S5, where the information of 0'' is the specific magnetic domain position of the liner loop 201.

By controlling the movement of information in the selected chip unit in this way, when any chip unit is not operating, the information at address “0” in the chip unit will be transferred to the liner loop 201 near the memory gate 202. This means that they exist at specific magnetic domain positions P255 and P2S5.

By controlling the movement of the magnetic domains in this manner, the control device can be used in common for all chip units, making the control device simple.

Next, a storage device that enables movement of magnetic domains as shown in FIG. 2 will be explained.

FIG. 3 shows an embodiment of a storage device according to the present invention using a magnetic bubble element.

A storage device using a magnetic bubble element, as shown in Fig. 1, consists of a substrate on which a chip unit of the magnetic bubble element is mounted, a memory section consisting of a rotating magnetic field coil, a bias magnetic field magnetic circuit, etc., and a rotating magnetic field drive circuit. It includes direct peripheral circuits consisting of sense circuits and gate circuits, and control devices for controlling the direct peripheral circuits.

In FIG. 3, the memory section is divided into multiple chip units to which a rotating magnetic field is simultaneously applied, and the memory section 1
1, memory section 12, . . . is closed.

A rotating magnetic field drive circuit 21 is provided for each divided memory section.
, a rotating magnetic field drive circuit 22A... are provided.

The sense circuit 30 amplifies and shapes the three detection signals generated from each memory section, and the gate circuit 40 supplies gate current to gates such as a write gate, a memory gate, and an erase gate of each chip unit in each memory section.

The connections 2 between the sense circuit 30 and the gate circuit 40 and the chip unit in the memory section vary depending on the storage device configuration, and are not directly related to the gist of the present invention, so they will be omitted.

Regarding storage device configuration, IEEE Transactions on Magnetics (IEEE T
transactions on Magnetics)
vol, MAG-8, pages 564 to 569. Note that the bias magnetic field magnetic circuit of the memory section may be provided independently in each memory section, or may be provided in common to multiple memory sections. Sometimes.

In FIG. 3, the portions other than the memory section and direct peripheral circuits are part of the control device of the storage device.

This part mainly performs control operations such as selecting a memory section, selecting a chip unit in the selected memory section, and controlling the movement of information at a specific address in the chip unit to stop at a specific magnetic domain position among the magnetic domain positions. This is a related part.

Address information input from the terminal 50 and fixed information input from the terminal 51 are set in the register 52.

Note that the fixed information is set in the lowest part of the register 52.

The role of fixed information will be explained later.

The decoder 53 uses the upper part of the address information from the register 52 as an input signal, and uses the rotating magnetic field drive circuits 21, 22 .
Give the output signal to...

Among the output signals, only the signal sent to the rotating magnetic field drive circuit corresponding to the selected memory section becomes "1".

For example, two sets of sinusoidal currents equal to the period of the clock pulse are supplied to the coil of the selected memory section from the rotating magnetic field drive circuit given the "1" input input bone, so that the coil rotates within the selected memory section. A magnetic field is generated, allowing movement of magnetic domains, or information.

The chip selection signal generating section 54 uses the middle part of the address information from the register 52 as an input signal, and provides an output signal for selecting a chip unit in the selected memory section to the sense circuit 30 and the gate circuit 40.

Comparator 61, flip-flop 62, gate 63
, counter 64, switch 65, and switch 66 constitute a first control section, and comparator 71, flip-flop 72, gate 73, counter 74, switch 75
, and switch 76 constitute a second control section.

Information consisting of the low-order part of the address information and fixed information from the register 52 is inputted from the terminal 652, and information determined depending on the configuration of the chip unit is inputted from the terminals 653, 752, and 753.

This allocation of address information is just one example, and the allocation can be made arbitrarily.

Note that when each memory section includes only one chip unit, it is not necessary to allocate address information to the middle portion.

Note that the switches 65, 66, 75, and 76 can actually be realized by semiconductor logic elements.

Further, the number of switches 65 and 75 is equal to the number of input bits of comparator 61 and comparator 71, respectively.

A clock pulse generator 56 provides clock pulses to the first control section and the second control section.

The memory gate operation signal generating section 57 gives a command to the gate circuit 40 to transfer information from the liner loop to the major loop using a signal given from the terminal 662 of the switch 66 of the first control section. A signal given from the terminal 763 of the switch 76 sends a command to the gate circuit 4 to transfer information from the major loop to the liner loop.
Give to 0.

A gate current is supplied from the gate circuit 40 to the memory gate of the chip unit at an appropriate timing in accordance with these instructions.

The write operation signal generating section 58 is connected to the switch 7 of the second control section.
In accordance with a command given from the terminal 762 of 6, a signal is given to the gate circuit 40 from the input section of the chip unit at the time of writing to instruct the operation of generating a magnetic domain array according to the written information.

In accordance with this command, gate current according to the write information is supplied from the gate circuit 40 to the write gate.

Next, the operation of a storage device using a chip unit having the structure shown in FIG. 2 will be explained, focusing on the read operation.

FIG. 2 can be considered as illustrating the movement of information in a selected chip unit within a selected memory portion specified by the upper and middle portions of the address information within the storage device.

This will be explained with reference to the state of the control device in FIG. 3 shown on the right side of FIG.

Since there are 127 addresses in the selected chip unit counting from O, the number of bits in the lower part of the address information is 7 bits.

If 2n bits of information belonging to an arbitrary address within the chip unit are continuously stored in each liner loop, n bits of fixed information that is "0" is stored at the terminal 51 in the lower part of the lower part of the address information. Add from.

From the specific example shown in FIG. 2, n=1.

Hereinafter, the address within the chip unit will be simply referred to as an address.

Also, even if the numbers in the storage device are expressed in binary numbers,
The explanation will be expressed in decimal numbers.

The operation of reading the information at address "3" of the selected chip unit in the selected memory section will be sequentially explained.

(1) First, initialize the storage device.

Clear the counter 64 and the counter 74 to make the contents zero. - The connection state of the switch 65, switch 66, switch 75, and switch 76 is as shown in FIG.

Note that the numerical value 512 is always given from the terminal 653, and the numerical value 256 is always given from the terminal 753.

These numerical values are determined by the configuration of the chip unit shown in FIG.

The numerical value given from the terminal 752 is a value determined by the position of the input section of the chip unit, but since only the reading operation will be explained, specific values will not be shown.

However, this value is generally smaller than 256.

The terminal 652 is given the lower part of the address information from the register 52, that is, the numerical value 6 (00000110) consisting of address information and fixed information within the chip unit.

At this time, in the chip unit, information of address "O" is located at magnetic domain positions P255 and P2S5 of the liner loop 201 (FIG. 2a).

2) When the flip-flop 62 is set by the operation command signal input from the terminal 55 and the gate 63 is opened,
The clock pulses are generated by the rotating magnetic field drive circuits 21, 22 .・・・
・Join in.

As a result, a rotating magnetic field is generated in the memory section selected by the drive circuit selected by the decoder 53, and the magnetic domain, ie, information, of the selected memory section begins to move.

Also, since the clock pulse becomes the input to the counter 64,
The contents of the counter 64 increase by one per period of the rotating magnetic field.

Address “3” of the chip unit of the selected memory section
The information reaches the magnetic domain positions P255 and P2S5 of the liner loop 201 after six magnetic field cycles.

(Figure 2b). At this time, the content of the counter 64 becomes 6, so a "1'output" is generated from the comparator 61, and a signal is applied from the memory gate operation signal generating section 57 to the gate circuit 40.

In accordance with this signal, a gate current is supplied from the gate circuit 40 to open the memory gate of the selected chip unit over the next two cycles.

As a result, the information at address “3” is stored in the memory gate 202.
The data is transferred from the liner loop 201 to the major loop 200 via .

Information at address "3" is detected by the major loop 200 and becomes read information.

3) Since the "1" output from the comparator 61 sets the flip-flop 72, the content of the counter T4 increases by one.

After the comparator 61 outputs "1", the terminals 651 and 653 of the switch 65 are connected, and the switch 66 connects the terminals 661 and 663.

While the information at address "3" circulates through the major loop 200 and is detected, the switch 75 connects the terminal 751 and the terminal 7.
53 is in a connected state, and in the switch 76, the terminal 161 and the terminal 763 are in a connected state.

When the information of address "3" reaches the magnetic domain positions P1 and P2S5 of the major loop 200 (Fig. 2 e) + counter 7
Since the content of 4 is 256, the comparator 71 outputs "
1″ output is generated and the memory gate operation signal generator 57
A signal is applied to the gate circuit 40 from.

A gate current is supplied from the gate circuit 40 to open the memory gate of the selected chip unit over the next two cycles.

At this time, since the information at address "3" has reached the magnetic domain positions P255 and P2S5 of the liner loop 201, the information at address "3" is transferred from the major loop 200 to the liner loop 201 via the memory gate 202.

(4) Since the numerical value 512, which is twice the number of bits of the liner loop 201, is input from the terminal 653, the address "
When the information of 0'' circulates through the liner loop 201 twice from the state shown in FIG. 61 generates a "1" output.

As a result, the flip-flop 62 is reset, the gate 63 is closed, and no clock pulse is applied to the rotating magnetic field drive circuit.

Therefore, the rotating magnetic field is no longer applied to the selected memory area where the magnetic domain was moving due to the rotating magnetic field being applied.
The movement of the magnetic domain stops, and the information at address "0" stops at the magnetic domain positions P255 and P2S5 of the liner loop 201.

Furthermore, the flip-flop 72 is kept in a reset state.

The operation of reading information at address "3" in the selected chip unit of the selected memory section of the storage device is thus completed.

In this way, the information of the address "0" which is the information of the specific address in the selected chip unit is the magnetic domain position P2 of the liner loop 201 which is the specific magnetic domain position before and after the operation.
55 and P2S5.

Similar conditions exist in other liner loops in the selected chip unit that are not shown.

In addition, the magnetic domain is also moved in the unselected chip unit of the selected memory section, but the information of the address "0" of this chip unit exists at the magnetic domain positions P255 and P2S5, which are specific magnetic domain positions, as before the operation. are doing.

In the storage device, when information is not being moved, the information at address "0" in any chip unit stops moving at magnetic domain positions P255 and P2S5 of the liner loop, and exists at these magnetic domain positions. are doing.

Therefore, no matter which chip unit is selected,
It is possible to select and read information at a specific address in the chip unit selected by the control device shown in FIG. 3, or to write to that address.

When writing new information to address "3" in the selected chip unit in the selected memory section, the information to be erased existing at address "3" is written in the same process as when reading the information. , are transferred from the liner loop 201 to the major loop 200, and are erased in the major loop 200.

At the same time, 200 major loops of magnetic domains corresponding to new information are inserted from the input section of the selected chip unit.

The period of the rotating magnetic field from when the information to be erased is transferred from the liner loop 201 to the major loop 200 until when new information begins to be inserted from the input section in the selected memory chip is determined by the input from the terminal 752. It is a numerical value.

Controlled according to this value, new information is transferred to the liner loop through the state of FIG.

The storage device of the present invention has been described above, taking as an example a magnetic storage device using a magnetic bubble element.

When the magnetic domain representing information is moved in units of memory units, the information at the specific address "θ" in the chip unit is controlled to stop moving at specific magnetic domain positions, for example, magnetic domain positions P255 and P2S5 in FIG. It is sufficient to provide a control device on one side for a plurality of memory units, contributing to the realization of a low-cost storage device.

Note that the storage device described above is not limited to the one shown in FIG. 3, but has various modifications.

For example, switch 65, switch 66, switch 75,
Also, a storage device including a control device that does not include the switch 76 but has four sets of control units each consisting of a comparator, a flip-flop, a gate, a counter, etc. can also be considered as an embodiment.

Furthermore, depending on the storage device configuration of the storage device shown in FIG. 3, there are various operations of the memory section and direct peripheral circuits.

In addition to address “0” as information on a specific address,
For example, if the information at specific addresses such as addresses "o", "64", and "128" is controlled to stop at specific magnetic domain positions, the operating speed of the storage device can be increased.

In this case, for example, in the memory unit 11, information of the address “θ” exists at the specific magnetic domain positions P255 and P2S5, whereas in the memory unit 12, information on the address “θ” exists at the specific magnetic domain positions P255 and P2S5.
5 and P2S5 may contain information for address "128".

Along with this, the control device that controls the stopping of information movement at a specific location among the locations where information at a specific address can exist has a part that is common to the memory part and a part that is unique to the memory part. It turns out.

However, by limiting the number of information for a specific address,
Specific to the memory section.

The control device part can be simplified.

The storage device according to the present invention includes a magnetic bubble element having variously modified M/m type chip configurations, a magnetic bubble element other than the M/m type chip configuration, and a magnetic bubble whose magnetic domain is moved by a conductor and a current flowing through the conductor. elements, magnetic domain storage elements other than magnetic bubble elements, MOS shift registers, CC
It can also be configured with a shift register type storage element that moves information, such as a semiconductor storage element such as D, and is not limited to a storage device using a magnetic bubble element with an M/m chip configuration.

[Brief explanation of the drawing]

FIG. 1 shows the chip configuration of the magnetic bubble element used in the storage device of the present invention, FIG. 2 shows the movement of magnetic domains in the magnetic bubble element, and FIG. 3 shows the structure shown in FIG. 1 is an embodiment of a storage device of the present invention using a magnetic bubble element. In FIG. 3, 11 and 12 are memory sections, 21 and 22 are rotating magnetic field drive circuits, 30 is a sense circuit, 40 is a gate circuit, 52 is a register for setting address information and fixed information from a terminal 50, and 53 is a register for setting address information and fixed information. The decoder 54 is a chip selection signal generator, and the other elements are a control device that controls the movement of information at a specific address to stop at a specific position.

Claims (1)

[Claims] 1. A storage device that selectively moves information within a storage element that moves information during read/write operations, including a control device that controls the movement of information at a specific address to stop at a specific position within the storage element. A storage device characterized by: