JPS5846638A - Reactive ion etching device - Google Patents

Reactive ion etching device

Info

Publication number
JPS5846638A
JPS5846638A JP14379581A JP14379581A JPS5846638A JP S5846638 A JPS5846638 A JP S5846638A JP 14379581 A JP14379581 A JP 14379581A JP 14379581 A JP14379581 A JP 14379581A JP S5846638 A JPS5846638 A JP S5846638A
Authority
JP
Japan
Prior art keywords
anode
cathode
reactive ion
etching
ion etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14379581A
Other languages
Japanese (ja)
Inventor
Hiroshi Takeuchi
寛 竹内
Toru Watanabe
徹 渡辺
Masahiro Shibagaki
柴垣 正弘
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP14379581A priority Critical patent/JPS5846638A/en
Publication of JPS5846638A publication Critical patent/JPS5846638A/en
Pending legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

PURPOSE:To enable the reactive ion etching device which generates no residue and shapes a pattern having high accuracy by forming an opening section by a concave section or a through port to an electrode at the ground side, giving plasma discharge a hollow effect and improving the degree of dissociation. CONSTITUTION:A cathode 2 is fitted to a reaction vessel 1 grounded, and a high-frequency power supply 3 in 13.56MHz is connected through a matching circuit 4. An anode 5 oppositely forming parallel plate electrodes is grounded, and a workpiece 7 is placed onto a carbon board 6 on the surface of the cathode 2. The cathode 2 or the anode 5 is turned during etching in order to obtain the uniformity of a wafer. The anode 5 has a 50cm diameter, and the concave section 5' having a 6mm. diameter and 12mm. depth is shaped at the center. When the total flow rates of CF3Br and Cl2 are made 30SOCM and a phosphorus doped poly-Si film formed onto the silicon wafer 20 in the figure a through CVD through a thermal silicon oxide film 21 under the states of a 60% Cl2 flow rate ratio, 0.1 Torr total pressure and 0.3w/cm<3> high-frequency power is etched while using a photo-resist as a mask, an etching profile in which there is no residue and undercut in the figure b is obtained.

Description

【発明の詳細な説明】 本発明は半導体素子等のパターン形成に用いる反応性イ
オンエツチング装置に関する。    ゛近年半導体素
子特にLSIや超L8Iの製造プロセスでは反応性イオ
ンを用いてパターンを形成する方法が注目され41}κ
高精度なパターンを形成する装置自体についても研究開
発がなされている。中でもパターンを形成すべき材料が
置かれた電極に高周波電力を印加することにより加工室
内に導入し九滅圧状態の反応性ガスをグロー放電(低温
プラズマ放電とも盲う)させる方法がある。この時高周
波電極にはプラズマ放電により生じた電子とイオンの易
動度の差に基づき、電位が隣下し負の自己バイアスが生
じる.この負の自己バイアスは基4ii降下電圧と呼ば
れ接地電位から計測してVdcで示され装置の電極形状
等によっても変化する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a reactive ion etching apparatus used for forming patterns of semiconductor devices and the like.゛In recent years, methods of forming patterns using reactive ions have attracted attention in the manufacturing process of semiconductor devices, especially LSIs and ultra-L8Is41}κ
Research and development is also being carried out on the device itself for forming highly accurate patterns. Among these methods, there is a method in which high-frequency power is applied to an electrode on which the material to be patterned is placed, thereby introducing the reactive gas into the processing chamber and causing a glow discharge (also referred to as low-temperature plasma discharge) of a reactive gas at zero pressure. At this time, the potentials of the high-frequency electrode are adjacent to each other, resulting in a negative self-bias, based on the difference in mobility between electrons and ions caused by plasma discharge. This negative self-bias is called a base voltage drop, is measured from the ground potential, and is expressed as Vdc, and varies depending on the shape of the electrodes of the device, etc.

エッチャントであるプラズマ中の正イオンはこのMac
により加速され被エッチング園を照射し、これと反応し
てガス化され系外に排気される。
The positive ions in the plasma, which is an etchant, are
It accelerates and irradiates the area to be etched, reacts with the irradiation, becomes gasified, and is exhausted out of the system.

従来用いられている反応性イオンエツチング装置の断面
図を示す。エツチング装置反応容器(1)には為周波電
極が設けられこれを以下陽極(2)と称す。
1 shows a cross-sectional view of a conventionally used reactive ion etching apparatus. The etching apparatus reaction vessel (1) is provided with a frequency electrode, hereinafter referred to as an anode (2).

この陰極{2}には13.56MHzの高周波電源(3
)がマツチング回路(4)を介して接続されている。前
記嬢* (2)とで平行平板電極を為すように対向して
接地された陽極(5)が設けられている。陰極(2)表
面にはカーボン板(6)を載置して、その上に被エツチ
ング物が設置される。反応家(1)内に設けたガス尋人
口(8)から反応性ガスを尋人し排気口(9)から排気
して乍ら陽極(2)に高周波電力を印加することによ!
ll均一なグロー放電(プラズマ放電) (11が発生
し反応性イオ/ニップ/グが行なわれる。
This cathode {2} is connected to a 13.56MHz high frequency power source (3
) are connected via a matching circuit (4). A grounded anode (5) is provided opposite to the above-mentioned electrode (2) so as to form a parallel plate electrode. A carbon plate (6) is placed on the surface of the cathode (2), and the object to be etched is placed on top of the carbon plate (6). By applying high-frequency power to the anode (2) while expelling the reactive gas from the gas outlet (8) provided in the reactor (1) and exhausting it from the exhaust port (9).
A uniform glow discharge (plasma discharge) (11) is generated and reactive ions/nip/g is performed.

酸化シリコン(SiOx)をエツチングし、コンタクト
孔を開ける場合にはCF4+ )I、 、 CHF、を
用いる事により良好なエツチングが出来る。
When etching silicon oxide (SiOx) to form a contact hole, good etching can be achieved by using CF4+)I, CHF.

単結晶シリコン(Si)や多結晶シリコン(poly 
−S i )特に不純物が絵加されたpoly −8i
を他の材料、例えば810.に対してパターン精度良く
藺いエツチング選択性を以ってエツチングするのは峻か
ったが、CBrF烏十C1,ガスを用いる事によシこれ
らの問題は一応解決された。
Single crystal silicon (Si) and polycrystalline silicon (poly
-S i) poly -8i with especially added impurities
other materials, such as 810. Although it was difficult to perform etching with good pattern accuracy and high etching selectivity, these problems were solved to some extent by using CBrF C1 gas.

然しなからpoly−8i特に燐(P)等の不純物が添
加されたpoly −S i特有のエツチング残渣も時
々発生し、これを除去するには、CF、Brに対しCj
m流量比を増加することで軽減可屈となったが、新たK
mテーパーヤアンダーカットが生じる問題が生じ九、こ
の様な理由によシ加工精度を保持するたメニ、少々のエ
ツチング残渣は犠牲にしていたが、近年LSI素子に見
られる^密度化した素子では、わずかなエツチング残渣
が電子の欠陥の原因となシ大きな問題となってきた。
However, etching residues peculiar to poly-8i, especially poly-Si to which impurities such as phosphorus (P) are added, sometimes occur, and in order to remove them, Cj
The reduction in flexibility was achieved by increasing the m flow rate ratio, but the new K
For this reason, in order to maintain machining accuracy, a small amount of etching residue has been sacrificed, but in recent years, the density of elements seen in LSI devices has increased. However, even small amounts of etching residue can cause electron defects, which has become a major problem.

本発明は上記事情に繊みて為されたもので、反応性イオ
ンニップフグにおけるpoly−8iのエツチング残渣
がエツチング装置構造に起因するプラズマ放電状緒に関
係することを見出し鋭意研究を重ね九緒釆、平行平板電
極の一万で6る接地1iIl電極に凹部もしくは貫通口
による開口Sを設はプラズマ放電にホロー効果を持たせ
ることにより解離度を良くすることにより、残渣の全く
生じないpoly−8i等の^精度なパターン形成を可
能にした反応性イオンエツチング装置を提供するもので
ある。
The present invention was developed in consideration of the above circumstances, and after extensive research, it was discovered that the poly-8i etching residue in the reactive ion nip puffer is related to the plasma discharge behavior caused by the structure of the etching device. , a parallel plate electrode with a grounded 1iIl electrode has an opening S formed by a recess or a through hole, which gives a hollow effect to the plasma discharge and improves the degree of dissociation, resulting in poly-8I that does not generate any residue. The object of the present invention is to provide a reactive ion etching device that enables highly accurate pattern formation.

以下、本発明を実施例により図面を参照して説明する。Hereinafter, the present invention will be explained by way of examples with reference to the drawings.

@211は本発明の実施例を示し、反応容器+1)には
陰極(2)が設けられ、13.56MHzの高周波電源
(3)がマツチング回路(4)を介して接続されている
。対向して平行平板電極を構成する陽極(5)は接地さ
れ、陰極(2)表面にはカーボン板(6)を載置してそ
の上に被加工物が設置される。向、容器(1)もアース
される。陰極(2)はウヱハー内、ウニI・−関の均一
性を得る丸めにエツチング中回転するようにされている
。陽極(5)を回転するようにしても良い。(8)はガ
ス導入口、(9)は排気口、Uυは冷媒パイプである。
@211 shows an embodiment of the present invention, in which a reaction vessel +1) is provided with a cathode (2) and connected to a 13.56 MHz high frequency power source (3) via a matching circuit (4). Anodes (5) facing each other forming parallel plate electrodes are grounded, and a carbon plate (6) is placed on the surface of the cathode (2), on which a workpiece is placed. On the other hand, the container (1) is also grounded. The cathode (2) is rotated within the wafer during etching to obtain rounding uniformity. The anode (5) may also be rotated. (8) is a gas inlet, (9) is an exhaust port, and Uυ is a refrigerant pipe.

陽極(5)は501極で、その中央に16E径6關、深
さ12鵡の凹部(5)が設けられている。
The anode (5) is a 501 pole, and a recess (5) with a diameter of 16E, 6 inches and a depth of 12 inches is provided in the center.

ココで、Ck’@に3rと(j、の全流量を30110
0Mとし、Cjffi流量比60騒、全圧力Q、ITo
rr 、高周波電力o、3w/ctAで第3図(a)の
シリコンウェハー(至)上に熱酸化シリコン膜Q1を介
してCVD形成したリンドープpoly−8+膜(60
00λ厚)を7オトレジストをマスクにしてエツチング
すると、第3図(b)に示す如く、残渣やアンダーカッ
トのないエツチングプロファイルが得られえ。
Here, add 3r to Ck'@ and the total flow rate of (j) to 30110
0M, Cjffi flow rate ratio 60 pm, total pressure Q, ITo
A phosphorus-doped poly-8+ film (60°
00λ thickness) using a 7-photoresist as a mask, an etching profile without residue or undercut can be obtained as shown in FIG. 3(b).

第3図(C)は全流量30aOOMで、C’wa量比6
0%。
Figure 3 (C) shows a total flow rate of 30aOOM and a C'wa amount ratio of 6.
0%.

0.1Torr 、 0.3w/d テ、従来tafl
 K ヨb 工y f /fした断面図である。アンダ
ーカットはないが柱状の*dl@が生じた。
0.1Torr, 0.3w/d TE, conventional TAFL
It is a sectional view taken by K yb machining y f /f. Although there was no undercut, columnar *dl@ was generated.

又、第3図(d)は同じ〈従来fj置でC12流量比8
0鴨で同様にパターン形成した時の断面図で、第3図(
C)の残渣(2)は−められないが、逆テーパ状のアン
ダ グーカット(2)が生じている。
Also, Fig. 3(d) shows the same <C12 flow rate ratio 8 at conventional fj position.
Figure 3 (
Although the residue (2) of C) is not visible, an undergoo cut (2) in a reverse tapered shape is formed.

第3図(−では、被加工物は4インチウェハーであり、
陰極(2)中央から201の位置に円形に並べられ九、
この様に、陽極(5)に凹部を設ける事により、ホロー
効果が生じプラズマの解離度が増し、残渣の発生が防止
出来る。凹部Fi陽極(5)の中央に設ける昼餐はなく
、ウェハーの対向部に設けても構わないものである。
In Figure 3 (-, the workpiece is a 4-inch wafer;
Cathode (2) arranged in a circle at a position of 201 from the center;
By providing the recess in the anode (5) in this manner, a hollow effect is generated, the degree of plasma dissociation is increased, and the generation of residue can be prevented. There is no need for a recess to be provided at the center of the recessed Fi anode (5), but it may be provided at the opposing portion of the wafer.

又、CFiBrとC1,の曹りにCFIBr + fi
r、を用いた場合に一同様に良好な結果が得られ友。
Also, as a substitute for CFiBr and C1, CFIBr + fi
Similarly good results were obtained when using r.

上記実施例では接置倒電極に1つの凹部を設は九例につ
いて述べ九が反応室の大自さ及び被エツチング物の面積
及び数量により数多くの凹部を設けても良く、また接地
電極に貫通口を開は真空的に封じ九反応装置においても
本発明は有効であった。この場合数個の貫通口を設けた
場合にも同様の結果が帰られたことは言うまでもない。
In the above embodiment, one recess is provided in the ground electrode, but nine examples are described. However, depending on the size of the reaction chamber and the area and quantity of the objects to be etched, a large number of recesses may be provided, and the ground electrode may be provided with one recess. The present invention was also effective in a nine reaction apparatus in which the opening was vacuum sealed. Needless to say, similar results were obtained when several through holes were provided in this case.

又本発明の変形例として凹部又は貫通口の10部形状は
円形のみでなく第3図(a)〜(e)に示す様な形状で
も良い。
Further, as a modification of the present invention, the shape of the ten portions of the recess or through-hole is not limited to a circular shape, but may be shaped as shown in FIGS. 3(a) to 3(e).

開口部の径D+Fi開口央行きDlに対し、D、≦D。D, ≦D for the opening diameter D+Fi and Dl toward the center of the opening.

の関係にあることが解離度を尚める上で好ましく、関口
は#i極のどこに設けても良いが平行平板電極母稀襦径
D3に対し50D、≦D3である番がエツチングむらを
防止する上で良い。
It is preferable to have the following relationship in order to improve the degree of dissociation, and the Sekiguchi may be provided anywhere on the #i pole, but the number that is 50D and ≦D3 with respect to the diameter D3 of the parallel plate electrode matrix prevents uneven etching. Good for what you do.

又、開口部はガス導入口を兼ねても同等の結果に加えて
より一層残虐の発生を防ぐ為のものであるが、カーボン
板の他炭化水素系の有機フィルム例えばポリエステルフ
ィルム又はポリプロピレン。
In addition, the opening can also serve as a gas inlet to achieve the same result and to further prevent the occurrence of cruelty, but in addition to carbon plates, hydrocarbon-based organic films such as polyester films or polypropylene may be used.

イソポリプロピレン、ポリスチレン等の高分子フィルム
でも良く、これらカーボンを含むシートが有効である。
Polymer films such as isopolypropylene and polystyrene may be used, and sheets containing carbon are effective.

実用化に際して、さらに好遣しくは装置内壁からの金属
材料による汚染を防ぐため、CF4. C,F・等C−
FガスにHlを加え九ガスを予めプラズマ放電させるこ
とにより、テフロン系高分子膜を陽極全体に堆積させ九
−置とするとさらに良い。この高分子膜を第1図に番号
α罎で示す。
In practical use, CF4. C, F・etc.C-
It is even better to deposit a Teflon-based polymer film over the entire anode by adding Hl to the F gas and subjecting the gas to plasma discharge in advance. This polymer membrane is indicated by the number α in FIG.

以上説明したように本発明はエツチング残渣を防止する
場合に有効で、単結晶シリコン、多結晶シリコンの他非
晶質シリコン、シリコン基板上に形成されたMo、Ta
、W等の′を極配線に用いられる高融点金属又はそれら
高融点金属硅化物、中でも不純物を添加したものをエツ
チングするに有効であり、反応性ガスとしてCFIBr
 +(j、)他、CF’sBr+Srt、 OF、ij
r +I、 、 CF、CI−+ Mrt、 CF、C
j+CJ、 、 CF、Cj+I、。
As explained above, the present invention is effective in preventing etching residues, and is effective in preventing etching residues formed on monocrystalline silicon, polycrystalline silicon, amorphous silicon, and silicon substrates.
, W, etc. are effective for etching high-melting point metals used for electrode wiring or their high-melting point metal silicides, especially those to which impurities are added, and CFIBr is used as a reactive gas.
+(j,) and others, CF'sBr+Srt, OF, ij
r +I, , CF, CI-+ Mrt, CF, C
j+CJ, , CF, Cj+I,.

OF@l−41r、、 (J、l−4−(j!、 CF
、I+I、さらにはCF、8r 1CBr、、 011
相方を用いても本発明の効果は変らない。
OF@l-41r,, (J, l-4-(j!, CF
, I+I, and even CF, 8r 1CBr,, 011
Even if a partner is used, the effects of the present invention do not change.

【図面の簡単な説明】 第1図は従来の反応性イオンエツチング装置の#面図、
#I2図は本発明の実施例に使用した反応性イオンエツ
チング装置断面図、第3図(荀〜(d)は本発明の詳細
な説明する断面図、第4図は本°発すJの凹部又は貫通
口の平面図である。 図において、 l・・・反応容器、    2・・・陰 極、3・・・
高Mll波電源、     4・・・マツチングボック
ス、5・・・接地電極、     5・・・凹 部、6
・・・カーボン板、    7・・・被加工智、8・・
・ガス導入口、     9・・・排気口、lO・・・
プラズマ放電、lO・・・ホロー効果、11・・・冷媒
バ・イ4プ、12・・・絶縁材、13・・・高分子膜、 14・・・ダークスペースシール)’(M縁体)、加・
・・シリコン基板、   4・・・シリコン酸化膜、4
・・・多結晶シリコン、  ム・・・フォトレジスト。 代壇人 弁理士  則 近 愈 佑 他1名 第  1  図 第2図 第3図 第4 一19′;
[Brief explanation of the drawings] Figure 1 is a # side view of a conventional reactive ion etching device.
#I2 is a cross-sectional view of the reactive ion etching device used in the embodiment of the present invention, Figure 3 is a cross-sectional view explaining the details of the present invention, and Figure 4 is a recessed portion of the J formed by this invention. Or it is a top view of a penetration hole. In the figure, 1... reaction container, 2... cathode, 3...
High Mll wave power supply, 4... Matching box, 5... Ground electrode, 5... Recessed part, 6
...Carbon plate, 7...Workpiece intelligence, 8...
・Gas inlet, 9...exhaust port, lO...
Plasma discharge, lO...Hollow effect, 11...Refrigerant pipe, 12...Insulating material, 13...Polymer membrane, 14...Dark space seal)' (M edge body) , Canada
...Silicon substrate, 4...Silicon oxide film, 4
...Polycrystalline silicon, Mu...Photoresist. Representative Patent Attorney Yu Yu Chika and 1 other person Figure 1 Figure 2 Figure 3 Figure 4-19';

Claims (2)

【特許請求の範囲】[Claims] (1)互い゛に対向して配置さ゛れ九陽極及び高周波電
力が印加筋れる陽極から成る平行子VL1を極を偏え、
高周波電力が印加される前記陽極に被加工物が設置され
、上記電極間にプラズマを発生させる反応性イオンエツ
チング装置に於いて、陽極に対向する陽極面に凹部又は
貫通孔が設けられ、陽極又は陽極の少なくとも一方が回
転可能にされて成る事を%黴とする反応性イオンエツチ
ング装置。
(1) Polarize the parallel plate VL1 consisting of nine anodes arranged opposite to each other and an anode to which high-frequency power is applied;
In a reactive ion etching device in which a workpiece is placed on the anode to which high-frequency power is applied and plasma is generated between the electrodes, a recess or a through hole is provided in the anode surface facing the anode, and the anode or A reactive ion etching device in which at least one of the anodes is rotatable.
(2)凹部又は貫通孔−の開口径Dh開口の奥行龜DI
+平行平板電極径Dsは、へ≦鳥、  50D+≦L)
、である事を特徴とする特許 載の反応性イオンエツチング装置。
(2) Opening diameter Dh of the recess or through hole - Depth of the opening DI
+Parallel plate electrode diameter Ds is ≦Bird, 50D+≦L)
A patented reactive ion etching device characterized by:
JP14379581A 1981-09-14 1981-09-14 Reactive ion etching device Pending JPS5846638A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14379581A JPS5846638A (en) 1981-09-14 1981-09-14 Reactive ion etching device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14379581A JPS5846638A (en) 1981-09-14 1981-09-14 Reactive ion etching device

Publications (1)

Publication Number Publication Date
JPS5846638A true JPS5846638A (en) 1983-03-18

Family

ID=15347155

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14379581A Pending JPS5846638A (en) 1981-09-14 1981-09-14 Reactive ion etching device

Country Status (1)

Country Link
JP (1) JPS5846638A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6159833A (en) * 1984-08-31 1986-03-27 Hitachi Ltd Plasma treater
JPS6226821A (en) * 1985-07-29 1987-02-04 インターナショナル・ビジネス・マシーンズ・コーポレーション Rf sputter/etching apparatus
JPH06302548A (en) * 1993-04-14 1994-10-28 Nec Corp Manufacturing apparatus for semiconductor device
US5439524A (en) * 1993-04-05 1995-08-08 Vlsi Technology, Inc. Plasma processing apparatus

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6159833A (en) * 1984-08-31 1986-03-27 Hitachi Ltd Plasma treater
JPS6226821A (en) * 1985-07-29 1987-02-04 インターナショナル・ビジネス・マシーンズ・コーポレーション Rf sputter/etching apparatus
JPH0528894B2 (en) * 1985-07-29 1993-04-27 Intaanashonaru Bijinesu Mashiinzu Corp
US5439524A (en) * 1993-04-05 1995-08-08 Vlsi Technology, Inc. Plasma processing apparatus
US5503881A (en) * 1993-04-05 1996-04-02 Vlsi Technology, Inc. Method of processing a semiconductor wafer
JPH06302548A (en) * 1993-04-14 1994-10-28 Nec Corp Manufacturing apparatus for semiconductor device

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