JPS5845046B2 - Memory device selection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a device selection circuit for a volatile memory battery backup method in which non-selection of a memory device is used as a high-level device selection signal.

MOS memory devices are generally used as RAM memory elements for microprocessors, and when it is necessary to prevent stored data from volatilizing when the main power is turned off, a battery independent backup method is used to supply power from a spare battery. taken.

In this battery backup process for volatile memory, it is necessary to set the selection signal of the memory device to a non-selected state in advance and switch to power supply from the battery to prevent data from being erroneously rewritten when the main power is turned off.

This non-selected state is canceled after power is established after power is restored.

Regarding the selection control of memory devices during battery backup, there is no problem in controlling the selection from selection to non-selection using the power-off warning signal for devices whose selection signal is positive logic, but when the selection signal is at a high level, the device is in a non-selected state. Conventional memory devices have problems in terms of data retention reliability and battery power consumption.

1 and 2 show the main part configuration of a conventional device selection control circuit.

FIG. 1 shows a TTL logic 1 which has an output selection terminal and is configured as a totem pole output circuit.In addition to the device selection signal sD, a power-off notice signal Sp is manually input to the selection terminal, and the MOS
In order to guarantee a high level input to the memory device 2, the selection signal driving circuit has a pull-up resistor 3 to the backup power supply.

In this drive circuit, the logic 1
Since the leakage current flowing into the device 2 is considerably larger than the current flowing into the device 2, it is necessary to increase the battery capacity for battery backup.

Figure 2 shows a TTL gate logic 4 that turns off the gate using a device selection signal sD and a power-off warning signal S, and its output drives a discrete circuit 7 consisting of a transistor 5, a pull-up resistor 6, etc., and turns off the transistor 5. The selection signal driving circuit is configured to obtain a non-selected state.

Although this conventional circuit can extremely reduce the leakage current to the transistor 5, there is a problem in that the memory access operation speed when the power supply is normal is limited by the response characteristics of the transistor used.

Furthermore, since the logic 4 that operates under the main power supply has a totem pole output, there is a risk that the selection control output may malfunction during a transition period when the main power supply voltage drops, and the circuit configuration cannot be said to be highly reliable.

SUMMARY OF THE INVENTION An object of the present invention is to provide a memory device selection circuit that does not adversely affect normal device selection operations, ensures data retention during battery backup, and reduces battery power consumption.

FIG. 3 is a circuit diagram showing one embodiment of the present invention.

The power-off warning signal S, T has an open collector output.
It is input to the TL inverter logic 1, and a series circuit of a light emitting diode 8A of the first coupler 8 and a pull-up resistor 9 is connected to its output load.

On the other hand, the device selection signal sD is connected to the emitter of the phototransistor 8B of the photocoupler 8, and its collector has a pull-up resistor 10 and is connected to the MOS memory device 2.
It is used as a selection signal input section for

In this configuration, for normal device selection, the power-off warning signal Sp is at high level and the output of logic 7 is at low level, current flows through photocoupler 80 and light emitting diode 8A, and the base current control of phototransistor 8B The input of the device 2 changes depending on the selected state in which the device selection signal sD is held in the on state and becomes low level, and the non-selected state in which the device selection signal sD becomes high level.

When the main power supply is shut down, as shown in the time chart in Fig. 4, a power cutoff warning signal (
The phototransistor 8B of the photocoupler 8 changes from high level to low level (time ti) in FIG. 4b).
The total current is then cut off, and the device selection signal (FIG. 4C) is cut off by turning off the transistor 8B.

In this cut-off state, the device 2 is connected to the pull-up resistor 10.
Give a high level non-select input to .

To recover from a main power supply failure, the power cutoff notice signal Sp becomes high level at time t2 after a sufficient time has elapsed for the main power supply voltage to return to normal or upon detection of the voltage, and the phototransistor 8B is held in the on state. , return to normal device selection.

Therefore, when power is normally supplied from the main power supply, the phototransistor 8B of the first coupler is held in the on state, allowing selection control by the device selection signal, and during battery backup, the phototransistor is turned off and forced device 2 to a non-selected state.

What should be noted here is that during battery backup, the leakage current from the pull-up resistor 10 to the transistor 8B is extremely small, similar to the discrete transistor shown in FIG. 2, and the current is cut off to the light emitting diode 8A.
Battery power consumption can be reduced.

In other words, the battery can be made smaller and more densely mounted on a printed circuit board than in the conventional method.

In addition, the normal device selection is F1-) transistor 8.
B is kept in the on state and is not directly related to its responsiveness, and high-speed operation can be achieved by using totem pole output logic as the source of the device selection signal sD.

In addition, since the power-off notice signal Sp uses open collector logic 7 to control the base current of transistor 8B, there is no malfunction of logic 7 even when the main power supply voltage drops, and the non-selected state can be maintained reliably. Can be done.

As explained above, the present invention provides battery backup for a memory device in which the polarity of the memory device selection signal goes high when not selected, and the logic output of the device selection signal and the selection signal input section of the memory device are connected to each other. A transistor with a pull-up resistor is provided in between, and the base current of this transistor is controlled by a power-off warning signal as a device selection circuit, so data can be retained reliably during battery backup without affecting normal device selection. This has an excellent effect in reducing battery power consumption.

[Brief explanation of drawings]

1 and 2 are conventional memory device selection circuit diagrams,
Fig. 3 is a circuit diagram showing one embodiment of the present invention, and Fig. 4 is a circuit diagram showing an embodiment of the present invention.
It is a time chart for explaining the operation of the figure. 2...Memory device, 7...Open collector inverter logic, 8...Photocoupler, 9.10...Sol-up resistor, 11
...Transistor, 12...Open collector logic, SD...Device selection signal, S, ...Power cutoff notice signal.

Claims (1)

[Claims] 1 In a battery backup method in which the polarity of the memory device selection signal is held at high level when a volatile memory device is not selected, the main power supply voltage of the memory device becomes low level before the power supply voltage drops and the main power supply voltage returns to normal. There is an open collector inverter logic that inputs the main power cutoff notice signal that returns to high level after the main power is turned off, and a light emitting diode is connected with a pull-up resistor between the output of this inverter logic and the power supply, and the logic of the memory device selection signal. The output is an emitter input, and a photocoupler is connected to a phototransistor whose collector is connected with a pull-up resistor between the output and the selection signal input part of the memory device. A memory device selection circuit characterized in that the base current of the phototransistor is cut off to switch the transistor from an on state to an off state, and a selection signal input section of the memory device is held at a high level.