JPH0249327A - Malfunction prevention circuit - Google Patents
Malfunction prevention circuitInfo
- Publication number
- JPH0249327A JPH0249327A JP20080788A JP20080788A JPH0249327A JP H0249327 A JPH0249327 A JP H0249327A JP 20080788 A JP20080788 A JP 20080788A JP 20080788 A JP20080788 A JP 20080788A JP H0249327 A JPH0249327 A JP H0249327A
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- relay
- circuit
- power
- capacitor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000007257 malfunction Effects 0.000 title claims abstract description 11
- 230000002265 prevention Effects 0.000 title claims description 4
- 239000003990 capacitor Substances 0.000 claims abstract description 12
- 238000010586 diagram Methods 0.000 description 3
- 238000001514 detection method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Landscapes
- Relay Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明に、ゲート回路の出力信号によりリレーを駆動
する回路の誤動作を防止するものに関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for preventing malfunction of a circuit that drives a relay using an output signal of a gate circuit.
第２図ばゲート回路の出力信号によりリレーを駆動する
従来の回路図である。FIG. 2 is a conventional circuit diagram in which a relay is driven by an output signal of a gate circuit.
図において、ｆｉｌ Ｈ回路に電源を供給する電源装置
、（２）にこの電源装置により給電されるゲート回路で
、この場合、ＮＡＮＤ回路である。（３１）１３２は抵
抗、＋４１ｉ’！電源装置＋１１の出力電圧を一定に保
持する定電圧ダイオード、＋５１ｆｌトランジスタで、
ＯＮ時リレー（６１を附熱し、その接点１７）を閉じ
る。即ち、ＮＡＮＤ回路１２）の出力信号レベルを定電
圧ダイオード（４１が検出する。その検出結果に基づい
てトランジスタ（６１０ベースに対して電流を流し、リ
レー（６）を駆動する。In the figure, a power supply device supplies power to the fil H circuit, and (2) a gate circuit supplied with power by this power supply device, which in this case is a NAND circuit. (31) 132 is a resistance, +41i'! A constant voltage diode and +51fl transistor that maintains the output voltage of the power supply device +11 constant.
When ON, the relay (61 is heated and its contact 17) is closed. That is, the output signal level of the NAND circuit 12) is detected by the constant voltage diode (41). Based on the detection result, a current is caused to flow to the base of the transistor (610) to drive the relay (6).
今、 ＮＡＮＤ回路（２）の入力がＯのとき、その出力
は１であり、これにより定電圧ダイオード（４）を介し
て、トランジスタ（５１０ベースにベース電圧が印加さ
れる。従って、リレー（６１には電源装置ｆｉ＋から動
作電流が供給され、その接点（７）ヲ閉じる。次にＮＡ
ＮＤ回路の入力が１のとき、その出力ば０であるので、
トランジスタ（６）にベース電圧が印加されず、リレー
（６）は不動作となり、接点（７）ハ開路する。Now, when the input of the NAND circuit (2) is O, its output is 1, and as a result, the base voltage is applied to the base of the transistor (510) via the constant voltage diode (4). is supplied with operating current from the power supply fi+, and closes its contact (7).Next, NA
When the input of the ND circuit is 1, its output is 0, so
No base voltage is applied to the transistor (6), the relay (6) is inoperative, and the contact (7) is opened.
従来の回路に上記のように構成されているので、電源装
置が電源断となった場合、その過渡期においてＮＡＮＤ
回路の出力信号が誤信号となる恐れがあり、そのとき、
電源装置の出力がリレー（６）を動作されるに必安なレ
ベルであれば、誤動作を生じてしまう問題点があった。Since the conventional circuit is configured as described above, when the power supply is cut off, the NAND
There is a risk that the output signal of the circuit will be an erroneous signal, and in that case,
If the output of the power supply device is at a level necessary to operate the relay (6), there is a problem that malfunction may occur.
この発明は上記のような課題を解消するためになされた
もので、電源断時【リレーが誤動作しないようにするこ
とを目的とする。This invention was made to solve the above-mentioned problems, and its purpose is to prevent the relay from malfunctioning when the power is turned off.
この発明に係る誤動作防止回路に、電源断時にゲート回
路でめるＮＡＮＤ回路の電源電圧を一時的に保つコンデ
ンサ全段けたものである。The malfunction prevention circuit according to the present invention includes all stages of capacitors that temporarily maintain the power supply voltage of the NAND circuit in the gate circuit when the power is turned off.
この発明における誤動作防止回路に、トランジスタ金柑
いてリレー金駆動する回路の電源がリレーの動作レベル
以下に低下するまでＮＡＮＤ回路の電源をコンデンサに
て電圧保持する。In the malfunction prevention circuit of the present invention, the voltage of the power source of the NAND circuit is held by a capacitor until the power source of the circuit that drives the relay using the transistor falls below the operating level of the relay.
〔発明の実施例〕
以下、この発明の一実施例を図について説明する。第１
図において、ｉｌｌは電源装置、（２）ぼＮＡＮＤ回路
、（３）に抵抗、（４）は定電圧ダイオード、（５）に
トランジスタ、＋６１ Ｂ リレー、（７）はその接点
、＋９１［電源断時ＮＡＮＤ回路（２）の電源を一時保
持するコンデンサ、ｔ８）ｉコンデンサ（９）からの放
Ｋｔ流の逆流全防止するダイオードである。[Embodiment of the Invention] An embodiment of the invention will be described below with reference to the drawings. 1st
In the figure, ill is the power supply, (2) is the NAND circuit, (3) is the resistor, (4) is the constant voltage diode, (5) is the transistor, +61 B relay, (7) is its contact, +91 [power off This is a capacitor that temporarily holds the power supply for the NAND circuit (2) at the time of t8), and a diode that completely prevents the reverse flow of the Kt current discharged from the i capacitor (9).
以下この発明の動作について説明する。第１図において
、電源が正常時、コンデンサ（９）には充電が行なわれ
ている。電源装置ｉｌｌが断となった時に電源装ｆｉｔ
＋１１からＮＡ ＮＤ回路（２）への給電も断となる
が、コンデンサ（９）より放電電流全流しすことにより
、ＮＡＮＤ回路の電源を一定時間保持する。この一定時
間はリレー（６）の駆ｖＪ電圧の最小値より電源装置ｆ
ｉｌの出力レベルが小さくなる時間までの時間で良い。The operation of this invention will be explained below. In FIG. 1, when the power supply is normal, the capacitor (9) is being charged. The power supply will fit when the power supply ill is disconnected.
Although the power supply from +11 to the NAND circuit (2) is also cut off, the power to the NAND circuit is maintained for a certain period of time by allowing the entire discharge current to flow through the capacitor (9). This certain period of time is determined by the minimum value of the drive vJ voltage of the relay (6).
It may be the time until the output level of il becomes low.
従って、一定時間経過後、ＮＡＮＤ回路（２）の電源断
時にＮＡ ＮＤ回路（２）から誤出力が発生しても、リ
レー（６）を駆動するだけの電圧レベルがないため、リ
レー接点（７）が誤動作することはない。Therefore, even if an erroneous output occurs from the NAND circuit (2) when the power to the NAND circuit (2) is turned off after a certain period of time has passed, there is not enough voltage level to drive the relay (6), so the relay contact (7 ) will not malfunction.
以上のように、この発明ンこよれば、電源断時、ゲート
回路の電源をコンデンサの放電電流により一定時間保つ
ようにしたので、ゲート回路の誤出力によるリレーの誤
動乍金防止することができる。As described above, according to the present invention, when the power is cut off, the power to the gate circuit is maintained for a certain period of time by the discharge current of the capacitor, so it is possible to prevent malfunction of the relay due to erroneous output of the gate circuit. can.
第１図にこの発明の一実施例を示すリレー駆動回路の回
路図、第２図は従来の回路図である。
図において、ｉｌｌに電源装置、（２１はＮＡＮＤ回路
、（３）ハ抵抗、（４）は定電圧ダイオード、（６）ハ
トランジスタ、（６）にリレー、（７）はリレー接点、
（８）はダイオード、＋９１Ｈコンデンサである。
なお、図中、同一符号は同−又は相当部分を示す。FIG. 1 is a circuit diagram of a relay drive circuit showing an embodiment of the present invention, and FIG. 2 is a conventional circuit diagram. In the figure, ill is a power supply device, (21 is a NAND circuit, (3) C is a resistor, (4) is a constant voltage diode, (6) is a transistor, (6) is a relay, (7) is a relay contact,
(8) is a diode and a +91H capacitor. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.
Claims (1)
と共通の電源が接続されたリレーの誤動作を防止する回
路において、上記電源により充電され、電源断により一
定時間上記ゲート回路へ給電するコンデンサを備えたこ
とを特徴とする誤動作防止回路。A circuit for preventing malfunction of a relay operated by an output signal of a gate circuit and connected to a common power source with the gate circuit, comprising a capacitor that is charged by the power source and supplies power to the gate circuit for a certain period of time when the power is cut off. A malfunction prevention circuit characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20080788A JPH0249327A (en) | 1988-08-10 | 1988-08-10 | Malfunction prevention circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20080788A JPH0249327A (en) | 1988-08-10 | 1988-08-10 | Malfunction prevention circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0249327A true JPH0249327A (en) | 1990-02-19 |
Family
ID=16430521
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20080788A Pending JPH0249327A (en) | 1988-08-10 | 1988-08-10 | Malfunction prevention circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0249327A (en) |
-
1988
- 1988-08-10 JP JP20080788A patent/JPH0249327A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4453194A (en) | Integrated power circuit with current sensing means | |
| JPS58140649A (en) | Voltage detecting circuit | |
| US5157270A (en) | Reset signal generating circuit | |
| JPH06208423A (en) | Power supply circuit | |
| US4208594A (en) | Power monitor for use in starting and stopping a digital electronic system | |
| JPH0249327A (en) | Malfunction prevention circuit | |
| JPH0421232Y2 (en) | ||
| JPH0326685Y2 (en) | ||
| KR880003147Y1 (en) | An alarm | |
| JPS5842971B2 (en) | Proximity switch | |
| JPH0143650Y2 (en) | ||
| JPH01303048A (en) | Discharge circuit | |
| JPH0326686Y2 (en) | ||
| KR930002080Y1 (en) | Driving circuit of solenoid for cardreader | |
| JP2831034B2 (en) | Inverter device | |
| JPS62138902A (en) | Microcomputer | |
| JPH0441368Y2 (en) | ||
| JPS5845046B2 (en) | Memory device selection circuit | |
| JPH04242316A (en) | Overcurrent detector circuit | |
| JPH0345854B2 (en) | ||
| KR890003753Y1 (en) | Automatic reset circuit in micro computer | |
| JPS6218007Y2 (en) | ||
| JPH0851771A (en) | Dc/dc converter with surge current limiting circuit | |
| JPS6338694Y2 (en) | ||
| JPS6028766A (en) | Gate controller of thyristor |