JPH0851771A - Dc/dc converter with surge current limiting circuit - Google Patents

Abstract

PURPOSE:To ensure the starting of operation of a main control circuit after completion of the charging operation of an input capacitor by providing an input surge current limiting circuit additionally on the input side of a DC/DC converter. CONSTITUTION:An AND circuit 17 comprises transistors 15, 16 generating an ON signal when both first and second signal circuits 10, 14 are operating. When the AND circuit is generating a signal, i.e., when the transistors 15, 16 are turned ON, a control circuit 18 is driven by a drive power supply through a transistor 19 and a resistor 20. The time constant of a timer circuit 7, determined by a capacitor 6 and a resistor 5, is set higher sufficiently than the charging time constant determined by the capacitor 4 and a resistor 2. Furthermore, a Zener diode 8 in the first signal generation circuit 10 is set higher than the gate threshold voltage of an FET 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for limiting an excessive current to an input capacitor, which is generated when an input hot line is inserted, in a DC / DC converter which operates by using a DC power source as an input.

[0002]

2. Description of the Related Art In a conventional circuit of this type of DC / DC converter, a resistor 2 and an FE inserted in series with an input line 1 are used.
A parallel circuit of T3 and a resistor 26 and a transistor 27 for turning off the FET 3 when the voltage of the resistor 2 is a certain value or more are generally arranged, and an example thereof is shown in FIG.

In this circuit, while the input capacitor 4 is being charged through the resistor 2, the FET generated by the voltage generated in the resistor 2 is used.
It operates so that 3 is turned off. However, if the main control circuit 18 starts to operate before the charging of the input capacitor 4 is completed, the FET 3 will not turn on forever because current continues to flow through the resistor 2 (2) Occurs. This defect is due to the fact that no signal is passed between the operation of the FET 3 and the operation of the main control circuit 18. Therefore, in this case, some kind of timer circuit for delaying the start of operation of the main control circuit 18 is required to solve the problem.

[0004]

It is an object of the present invention to provide an inexpensive alternative circuit which does not require a timer circuit for delaying the start of operation of the main control circuit.

[0005]

EXAMPLE FIG. 2 shows an example of the present invention. According to the present invention, a parallel circuit of a resistor 2 and a FET 3 is connected in series to an input line 1, an input capacitor 4 charged through the resistor 2 when an input hot line is inserted, a resistor 5 and a capacitor for turning on the FET 3 after a lapse of a certain time. A timer circuit 7 composed of 6; a Zener diode 8 set to a voltage higher than the gate-on voltage of the FET 3; and a first signal generating circuit 10 composed of a resistor 9; A second signal generating circuit 1 composed of a Zener diode 11, a resistor 12, and a resistor 13 for generating a signal when the value exceeds a specified value.
4 and an AND circuit 17 composed of a transistor 15 and a transistor 16 that generate an ON signal when both the first and second signal circuits 10 and 14 are operating,
When the signal of the AND circuit is generated, that is, when the transistors 15 and 16 are turned on, driving power is supplied to the control circuit 18 through the transistor 19 and the resistor 20. Reference numeral 21 is a diode for rapidly discharging the capacitor 6 of the timer circuit 7 to accelerate the reset operation.

In the embodiment of the present invention shown in FIG. 2, the time constant of the capacitor 6 and the resistor 5 of the timer circuit 7 is determined to be sufficiently larger than the charging time constant determined by the capacitor 4 and the resistor 2. Furthermore, the Zener diode of the first signal generation circuit 10
The gate 8 is set higher than the gate threshold voltage of the FET 3. (3)

The transformer 22, the FET 23, the diode 24 and the capacitor 25 constitute a main circuit of the DC / DC converter.

[0008]

The input inrush current limiting circuit of the present invention is DC /
By adding it to the input side of the DC converter, the main control circuit can surely start the operation after the charging of the input capacitor is completed, and it is possible to provide the DC / DC converter of stable operation.

[Brief description of drawings]

FIG. 1 DC / D having a conventional input inrush current limiting circuit
C converter

FIG. 2 is a DC / DC converter with an input inrush current limiting circuit according to the present invention.

[Explanation of symbols]

 1 Input Lines 2, 5, 9, 12, 13, 20, 26, 28 Resistors 3, 23 FETs 4, 6, 25 Capacitors 7 Timer Circuits 8, 11 Zener Diodes 10 First Signal Generation Circuits 14th 2 signal generation circuit 15, 16, 19, 27 transistor 17 AND circuit 18 main control circuit 21, 24 diode 22 transformer

Claims (1)

[Claims] 1. An input capacitor in which a parallel circuit of a resistor and a FET is connected in series to an input line, the input capacitor is charged through the resistor when the input hot line is inserted, and the FE after a lapse of a predetermined time.
A timer circuit for turning on T, a first signal circuit for generating a signal after the FET is turned on, a second signal circuit for generating a signal when the voltage of the input line is equal to or more than a specified value, and the second An AND circuit that produces an output when both signals of the first and second signal circuits are produced is provided, and the main control circuit operates when there is an output signal of the AND circuit, and when there is no output signal, the main control circuit operates. DC / DC with input inrush current limiting circuit characterized in that the control circuit is configured to stop
Converter.