JPH0373891B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a semiconductor memory device, and particularly to a complementary semiconductor memory device that can be backed up by an emergency power supply.

(2) Prior Art and Problems A conventional semiconductor memory device configured to be backed up by an emergency power source is shown in FIG. The power supply terminal VS of the semiconductor memory device MEM shown in _{FIG .} Connected.
Normal power supply V _cc1 outside the storage device MEM
A circuit DT for detecting a drop in the memory is provided, and the output of this detection circuit DT is connected to an external clock signal (for example, a chip select signal) that controls the entire memory.
CS) is input to the OR gate circuit OR, and the output of the OR gate OR is input to the memory control terminal MS of the storage device MEM.

In the circuit shown in FIG. 1, during normal operation, the voltage at the point is higher than the output voltage of the power supply _Vcc2 , so the diode _D2 is cut off, and the circuit is operated by the power supply current from the power supply _Vcc1 . Next, when the output voltage of the power supply V _cc1 drops for some reason, the diode D ₂ turns on, and the output voltage of the emergency power supply V _cc2 consisting of a battery, etc. starts to be supplied, and at the same time, the output voltage from the power drop detection circuit DT starts to be supplied. The output becomes high level, and the output of the OR gate circuit OR becomes high level regardless of the chip select signal, and the memory becomes in a static state. Therefore, the data in the memory is maintained without being destroyed even when the power supply voltage _Vcc1 decreases.

By the way, in the circuit shown in Figure 1,
It is necessary to provide a diode, an OR gate circuit, a power drop detection circuit, etc. outside the semiconductor memory device MEM, which poses a problem in that the circuit design and configuration become more complicated.

(3) Purpose of the Invention In view of the problems of the conventional type described above, the purpose of the present invention is to provide a semiconductor memory device with two terminals for normal and emergency use as power supply terminals, and to provide a special circuit externally. The object of the present invention is to enable backup retention of the memory even when the power supply voltage for normal use is reduced without the provision of such a memory.

(4) Structure of the Invention The present invention includes a power supply terminal for normal use, a power supply terminal for emergency use, a power supply voltage drop detection circuit that detects a drop in voltage applied to the power supply terminal for normal use, and a power supply voltage drop detection circuit that detects a drop in voltage applied to the power supply terminal for normal use; In response to the internal supply voltage,
A power supply voltage supply circuit that supplies a power supply voltage applied to the emergency power supply terminal in place of the power supply voltage applied to the normal power supply terminal, and controls switching between an operating state and a static state of the semiconductor memory device. a chip select signal terminal to which a chip select signal is input from the outside; a first stage inverter for inputting the chip select signal; and a first stage inverter for inputting the chip select signal;
a control signal generation circuit comprising: a first transistor that cuts off supply of the internal power supply voltage to the first-stage inverter; and a second transistor that fixes the output level of the first-stage inverter so that the semiconductor memory device is in a static state; and the control signal generation circuit changes the operating/quiescent state of the semiconductor memory device in response to the externally input chip select signal when the power supply voltage drop detection circuit does not detect a voltage drop. When switching is performed and the power supply voltage drop detection circuit detects a voltage drop, the semiconductor memory device is held in a static state regardless of the state of the externally input chip select signal. Equipment is provided.

(5) Embodiment of the Invention A semiconductor memory device as an embodiment of the invention is shown in FIG. In the semiconductor memory device of FIG. 2, a normal power supply V _cc1 and an emergency power supply V _cc2 are connected to two power supply terminals VS ₁ and VS ₂ , respectively. Power supply terminals VS ₁ and VS ₂ are connected to a connection point N1 via diodes D1 and D2 inside the integrated circuit. A power line from connection point N1 is connected to each circuit within the integrated circuit.

The semiconductor storage device shown in Figure 2 also has a normal power supply.
It has a built-in circuit DT that detects a voltage drop in V _cc1 . The power supply voltage drop detection circuit DT connects to the connection point N1.
Complementary MOS inverter connected between
_I1 , and the output voltage of the power supply _Vcc1 is input. An external clock signal (for example, a chip select signal) that controls the entire memory is input to the control signal generation circuit CS via the terminal MS. _The control signal generation circuit CS is composed of complementary MOS inverters I _{2 and I 3} as shown in FIG. A P-channel MOS transistor _T3 is connected, and an N-channel MOS transistor _T6 is connected between the output of the second inverter and ground. The P channel and N
The output of the voltage drop detection circuit DT is connected to the gate of each channel MOS transistor.

In the semiconductor memory device shown in FIG. 2, the normal power supply V _cc1 is connected to the power supply terminal VS ₁ so that diode D ₂ is reverse biased during normal operation.
An emergency power supply _Vcc2 is connected to _VS2 . Therefore power supply
When V _cc1 is normal, the input of the inverter I ₁ is at a high level, so its output is at a low level, and the P channel transistor T ₃ is turned on and the N channel transistor T ₆ is turned off. Therefore, the memory MEM operates according to the chip select signal. On the other hand, if the output voltage of the power supply V _cc1 decreases for some reason, the diode D ₂ becomes conductive and voltage is supplied from the emergency power supply V _cc2 . At this time the terminal
Since the potential of VS ₁ is low level, inverter I ₁
The output of becomes high level, and the MOS transistor
T ₃ is turned off and inverter I ₂ becomes inactive, and MOS transistor T ₆ is turned on and the input of inverter I ₃ becomes low level. Therefore, the output of the inverter _I3 is fixed at a high level regardless of the chip select signal, the entire memory is put into a static state, and the data in the memory is held without being destroyed.

Note that although the above description has been made using a complementary MOS memory as an example, the scope of application of the present invention is not limited to this.

(6) Effects of the Invention According to the present invention, in a semiconductor memory device, by separately connecting the normal power source and the emergency power source, the normal power source can be connected without providing a special circuit outside the integrated circuit. Memory backup can be maintained during voltage drops.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a conventional semiconductor memory device.
FIG. 2 is a circuit diagram of a semiconductor memory device as an embodiment of the present invention. (Explanation of symbols), MEM: semiconductor memory device, DT:
Power supply voltage drop detection circuit, CS: control signal generation circuit,
CS: Chip select signal.

Claims (1)

[Claims] 1: a normal power supply terminal VS ₁ ; an emergency power supply terminal VS ₂ ; a power supply voltage drop detection circuit DT that detects a drop in the voltage applied to the normal power supply terminal; In response to the detection, a power supply voltage supply circuit D ₁ , D supplies a power supply voltage applied to the emergency power supply terminal as an internal power supply voltage in place of the power supply voltage applied to the normal power supply terminal. ₂ , a chip select signal terminal MS to which a chip select signal for controlling switching between an operating state and a static state of the semiconductor storage device is inputted from the outside; first stage inverters T ₄ and T ₅ for inputting the chip select signal; In response to the detection, a first transistor T3 cuts off the supply of the internal power supply voltage to the first stage inverter, and a second transistor _T3 fixes the output level of the first stage inverter so that the semiconductor memory device is in a static state. and a control signal generation circuit CS comprising a transistor _T6 , and the control signal generation circuit responds to the externally input chip select signal when the power supply voltage drop detection circuit does not detect a voltage drop. When the semiconductor memory device is switched between the operating state and the rest state, and the power supply voltage drop detection circuit detects a voltage drop, the semiconductor memory device is switched regardless of the state of the externally input chip select signal. A semiconductor memory device that is maintained in a stationary state.