JPS5844842A - Digital signal transmission system - Google Patents
Digital signal transmission systemInfo
- Publication number
- JPS5844842A JPS5844842A JP56143260A JP14326081A JPS5844842A JP S5844842 A JPS5844842 A JP S5844842A JP 56143260 A JP56143260 A JP 56143260A JP 14326081 A JP14326081 A JP 14326081A JP S5844842 A JPS5844842 A JP S5844842A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- transmission
- circuit
- status
- synchronization
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/12—Arrangements providing for calling or supervisory signals
- H04J3/125—One of the channel pulses or the synchronisation pulse is also used for transmitting monitoring or supervisory signals
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
Description
【発明の詳細な説明】
本発明はデジタルデータ伝送においてデータに付随して
伝送されるステータス信号の伝送方式に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a transmission system for a status signal transmitted along with data in digital data transmission.
デジタルデータ伝送については種々の方式が実用化され
て伝るが、代表的な伝送方式として６４ｋｂ自／ｓｅｅ
の伝送速度を有するデジタルデータ伝送がある。これに
ついて概説すると、この伝送方式は同期用の同期パター
ン信号、端末装置の状態を表わすステータス信号、およ
びデータの３種類の情報を８ｂｉｔ一単位に分割して受
信側に伝送するものである。この８ｂｉｔの単位情報は
同期信号１ｂｉｔ、ステータス信号１ｂｉｔ、およびデ
〜り６ｂｉｔの割当てで使用される。通常、送信側では
同期パターン発□生装置からの同期信号を基準としてデ
ータ情報およびステータス情報を定められた順序に配列
構成し伝送路に送出する。一方、受信側では伝送路を介
して到来する送信デジタル信号を同期識別回路に引込み
同期パターン信号の有無状態を監視すふ。ここで、同期
パターンが識別されると受信信号をそれぞれ同期信号、
ステータス信号、およびデータの信号情報として分離し
て受信側端末装置に伝える。Various methods have been put into practical use for digital data transmission, but a typical transmission method is 64kb/see.
There is a digital data transmission with a transmission rate of . To summarize, this transmission method divides three types of information into 8-bit units: a synchronization pattern signal for synchronization, a status signal representing the status of the terminal device, and data, and transmits the divided information to the receiving side. This 8-bit unit information is used to allocate 1 bit of synchronization signal, 1 bit of status signal, and 6 bits of data. Normally, on the transmitting side, data information and status information are arranged and configured in a predetermined order based on a synchronization signal from a synchronization pattern generating device and sent to a transmission path. On the other hand, on the receiving side, the transmitted digital signal arriving via the transmission path is input to a synchronization identification circuit and the presence or absence of a synchronization pattern signal is monitored. Here, when the synchronization pattern is identified, the received signal is converted into a synchronization signal,
The status signal and data signal information are separated and transmitted to the receiving terminal device.
しか゛シ藩から、どのようなデジタル信号伝送方式にお
いては、ステータス信号の伝送用に常時１ｂｉｔを割当
てるため、実際に伝送できるデータ伝送量は６４Ｋｂｉ
ｔ／ｓｅｃ Ｘ ６ ／ ８ ＝ ４８Ｋｂｉ ｔ／ｓ
ｅｃとなシ、データ伝送量の低下を招かざるを得ない。However, in any digital signal transmission method, 1 bit is always allocated for transmitting the status signal, so the amount of data that can actually be transmitted is 64Kbit.
t/sec x 6/8 = 48Kbit t/s
EC, this inevitably leads to a decrease in the amount of data transmission.
本発明の目的は、ステータス信号の有無（ＯＮｌｏＦＦ
）状態に従って送受信装置間同期用の同期パターン信号
の論理を正あるいは負論理に反転させることにより、受
信側への同期パターン信号の伝送のみで同期信号情報と
ステータス信号情報とを得ることを可能としてデータ伝
送音を増大できるデジタル□信号伝送方式を提供するこ
とにある。The purpose of the present invention is to determine the presence or absence of a status signal (ONloFF).
) By inverting the logic of the synchronization pattern signal for synchronization between transmitting and receiving devices to positive or negative logic according to the state, it is possible to obtain synchronization signal information and status signal information only by transmitting the synchronization pattern signal to the receiving side. An object of the present invention is to provide a digital □ signal transmission method that can increase data transmission sound.
本発明によるデジタル信号伝送方式は、複数ビット１単
位構成で伝送されるデジタル信号の少なくとも１ビット
、に同期信号を割当て、且つ送信側の２値のステータス
状態に応じて前記同期信号を論理反転させてデータとと
もに複数組送出し、受信側において前記同期信号を逆論
理反転してステータス情報を得ることを特徴とする。The digital signal transmission method according to the present invention allocates a synchronization signal to at least one bit of a digital signal transmitted in one unit of multiple bits, and logically inverts the synchronization signal according to a binary status state on the transmitting side. The synchronizing signal is transmitted in plural sets together with data, and the receiving side inverts the logic of the synchronizing signal to obtain status information.
以下、図面を参照してこの発明の実施例について説明す
る。Embodiments of the present invention will be described below with reference to the drawings.
図はこの発明によるデジタル信号伝送方式の一実施例を
示す構成図である。図を参照して、データを伝送する際
の動作を順次説明すると、送信端末装置側より送出され
たデータＤＴはマルチプレクサ１００に入力され、且つ
ステータス信号ＳＴ８が排他的論理和回路（ＥＸ−ｏｉ
ｒゲー））１０４に入力される。ステータス信号８ＴＳ
と送信制御装置１０１によ多制御される同期パターン信
号発生回路１０２の出力信号とはＥＸ−ＯＲゲート１０
４にて排他的論理和演算される。このとき、同期パター
ン信号ＳＹＮはステータス信号Ｓ’ｌ’Ｓの０Ｎ１０Ｆ
Ｆ（“１′／４ｏ・）状態により論理反転されてマルチ
プレクサ１００に入力される。これにより、マルチプレ
クサ１００は送信制御装置１０１の制御に基いてデータ
ＤＴとＥＸ−ＯＲゲート１０４の出力の同期信号ＳＹＮ
とを所定の複数ビット構成に組合せて送信側伝送路イン
ターフェース回路１０３へ送出する。送信側伝送路イン
ターフェース回路１０３は入力された複数ビット１単位
構成のデジタル信号を伝送路の信号形態に適合するよう
に変換し、伝送路３００へ送出する。例えば、信号のユ
ニポーラ・バイポーラ変換を行なう。伝送路３００を介
して送られたイバ号は受信側伝送路インターフェース回
路２００により伝送路３００の信号形態から通常の論理
レベルの信号に変換され、デマルチプレクサ２０１およ
び同期識別回路２０３ 、２４０ に受信される。こ
の同期識別回路は正論理の同期パターン信号を識別する
正同期識別回路２０３と負論理の同期パターン信号を識
別する負同期識別回路２０４とを有し、これらの回路が
伝送路３００からの信号より同期パターンを識別する。The figure is a configuration diagram showing an embodiment of the digital signal transmission system according to the present invention. Referring to the figure, the operation when transmitting data will be explained sequentially. Data DT sent from the transmitting terminal device side is input to the multiplexer 100, and the status signal ST8 is input to the exclusive OR circuit (EX-oi).
r game)) 104. Status signal 8TS
The output signal of the synchronization pattern signal generation circuit 102 which is controlled by the transmission control device 101 is the EX-OR gate 10.
Exclusive OR operation is performed in step 4. At this time, the synchronization pattern signal SYN is 0N10F of the status signal S'l'S.
The logic is inverted by the F (“1′/4o・) state and input to the multiplexer 100.Thereby, the multiplexer 100 outputs a synchronization signal between the data DT and the output of the EX-OR gate 104 under the control of the transmission control device 101. SYN
and is combined into a predetermined multi-bit configuration and sent to the transmission line interface circuit 103 on the transmitting side. The transmission line interface circuit 103 on the transmission side converts the input digital signal, which is composed of multiple bits in one unit, to match the signal form of the transmission line, and sends it to the transmission line 300. For example, unipolar/bipolar conversion of the signal is performed. The signal sent via the transmission line 300 is converted from the signal form of the transmission line 300 to a normal logic level signal by the receiving side transmission line interface circuit 200, and is received by the demultiplexer 201 and the synchronization identification circuits 203 and 240. Ru. This synchronization identification circuit has a positive synchronization identification circuit 203 that identifies a positive logic synchronization pattern signal and a negative synchronization identification circuit 204 that identifies a negative logic synchronization pattern signal. Identify synchronization patterns.
今、仮に正論理の同期パターン（ｇ号が送信側より送ら
れているすなわちステータス信号ＳＴＳがｏｘ；’Ｆ（
”０″）状態の場合を考えると、正同期識別回路２０３
は同期パターンを識別し出力論理を”１″とする。この
出力信号はＯＲゲー ト２０５に入力され、Ｏ１′Ｌゲ
ート２０５の出力論理が”１″となる。これによシ、受
信制御装置２０２は同期がとれたことを識別し、デマル
チプレクサ２０１を制御して受信信号をデータＤＴと同
期信号ＳＹＮに分離して受信端末装置側に送出させる。Now, suppose that the positive logic synchronization pattern (g is sent from the transmitting side, that is, the status signal STS is ox;'F(
Considering the case of the “0”) state, the positive synchronization identification circuit 203
identifies the synchronization pattern and sets the output logic to "1". This output signal is input to the OR gate 205, and the output logic of the O1'L gate 205 becomes "1". As a result, the reception control device 202 identifies that synchronization has been achieved, and controls the demultiplexer 201 to separate the received signal into data DT and synchronization signal SYN and send them to the receiving terminal device side.
一方、負同期識別回路２０４は同期パターンを識別しで
５−
いない／Ｃめ、出力論理を０”とし、ステータス信号ｓ
’ｉ’ ｓ出力であるＯＲゲート２０８け“０＃レベ
ル信号を出力して受信端末装置側にステータス信号ＳＴ
８のＯＦＦ状態を表示する。逆に、負論理の同期倍旧が
送信側より送られているすなわちステータス信号ＳＴＳ
がＯＮ（”ｌ”）状態の場合には、正同期識別回路２０
３の出力は″′０＃レベルに、負同期識別回路２０４の
出力はパ１”レベルと々シ、ＯＲゲー）２０８は“１″
レベルを出力するため、ステータス信号ＳＴＳのＯＮ（
”ｌ”）状態を受信端末装置側は検出で、きる。なお、
同期識別回路２０３．２１３４ が両方とも同期識別を
できない時には、同期中と区別するために、インバータ
２０６、ＡＮＤゲート２０７、およびｏｉｔゲート２０
８の構成によってステータス４ｑ号８Ｔ８出力として非
同期表示信号Ｎ５ＹＮを出力させる。On the other hand, the negative synchronization identification circuit 204 identifies the synchronization pattern, sets the output logic to 0'', and outputs the status signal s.
The OR gate 208 which is the 'i' s output outputs the "0# level signal and sends the status signal ST to the receiving terminal device side.
Displays the OFF state of 8. Conversely, if a negative logic synchronization signal is sent from the transmitting side, that is, the status signal STS
is in the ON (“l”) state, the positive synchronization identification circuit 20
The output of the negative synchronization identification circuit 204 is at the "P1" level, and the output of the OR game) 208 is at the "1" level.
To output the level, turn on the status signal STS (
The receiving terminal device side can detect the “l”) state. In addition,
When both the synchronization identification circuits 203 and 2134 cannot perform synchronization identification, the inverter 206, AND gate 207, and oit gate 20
8 outputs the asynchronous display signal N5YN as the status 4q 8T8 output.
以上この発明の一実施例について述べたが、例えば６４
Ｋｂｉ ｔ ／ ｓｅｅの伝送速度で学位情報を８
ｂｉｔ構成にて伝送する場合、ステータス信号用の割当
てビットを要しなしため、同期信号１ｂｉｔおよび６一
データ７ピツトとして６４Ｋｂロ／ｓｅｃ Ｘ ７／８
＝５６Ｋｂｉ ｔ ／ ｓｅｃのデータ伝送を可能
にする。Although one embodiment of the present invention has been described above, for example, 64
Degree information at Kbit/see transmission speed
When transmitting in a bit configuration, there is no need to allocate bits for status signals, so 1 bit of synchronization signal and 7 bits of 6-data data are transmitted at 64 Kb/sec x 7/8.
=56Kbit/sec data transmission is possible.
本発明は以上説明のように、送信ｌｉｔステータス信号
の０Ｎ１０１？ Ｆ状態に従って同ＪＩ、ｌｊパターン
信号の論理を逆にすることにより、同期値１号にステー
タス信号をおり込んで受信側に伝送することが可能とな
り、所定範囲内の伝送容筒を有する伝送路におけるデー
タ自体の伝送着を増加できる。As explained above, the present invention provides the transmission lit status signal 0N101? By reversing the logic of the same JI and lj pattern signals according to the F state, it becomes possible to incorporate the status signal into the synchronization value No. 1 and transmit it to the receiving side, and it becomes possible to transmit the status signal to the receiving side, and it is possible to transmit the status signal to the receiving side. It is possible to increase the transmission capacity of the data itself.
図は本発明によるデジタル信号体送力式の一実施例を示
す構成図である。
ｌＯＯ・・・・・マルチプレク丈、１０１・・・・・送
信制御装置、１０２・・・・・・同期パターン発生回路
、１０３・・・・・・送信側伝送路インターフェース回
路、１０４・・・・・・排他的論理和回路、２００・・
・・・受信側伝送路インターフェース回路、２０１・・
・・・・デマルチプレクサ、２０２・・・・・・受信制
御装置、２０３・・・・・・正同期識別回路、２０４・
・・・・・負同期識別回路、２０５・・−・・・ＯＲゲ
〜ト、２０６・・・・・・インバータ、２（１７・・・
・・・ＡＮＩ）ゲート、２０８・・・・・・ＯＲゲート
、３ｏ。
・・・・−・伝送路。The figure is a configuration diagram showing an embodiment of the digital signal transmission type according to the present invention. lOO...Multiplex length, 101...Transmission control device, 102...Synchronization pattern generation circuit, 103...Transmission side transmission line interface circuit, 104... ...Exclusive OR circuit, 200...
...Reception side transmission line interface circuit, 201...
... Demultiplexer, 202 ... Reception control device, 203 ... Positive synchronization identification circuit, 204 ...
... Negative synchronization identification circuit, 205 ... OR gate, 206 ... Inverter, 2 (17 ...
...ANI) gate, 208...OR gate, 3o. ......Transmission line.
Claims (1)
少なくとも１ビツトに同期信号を割当て、且つ送信側の
２値のステータス状態に応じて前記同期信号を論理反転
させてデータとともに複数組送出し、受信側において前
記同期信号を逆論理□反転してステータス情報を・得る
ことを特徴とするデジタル信号伝送方式。Allocating a synchronization signal to at least one bit of a digital signal transmitted in one unit of a plurality of f bits, and inverting the logic of the synchronization signal according to the binary status state of the transmitting side, and transmitting and receiving a plurality of sets together with data. A digital signal transmission system characterized in that status information is obtained by inverting the synchronization signal on the side.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56143260A JPS5844842A (en) | 1981-09-11 | 1981-09-11 | Digital signal transmission system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56143260A JPS5844842A (en) | 1981-09-11 | 1981-09-11 | Digital signal transmission system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5844842A true JPS5844842A (en) | 1983-03-15 |
Family
ID=15334603
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56143260A Pending JPS5844842A (en) | 1981-09-11 | 1981-09-11 | Digital signal transmission system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5844842A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0269158A1 (en) * | 1986-11-26 | 1988-06-01 | ITALTEL TELEMATICA S.p.A. | Digital telephone switching exchange, particularly for private systems (PABX) |
| US5959240A (en) * | 1996-12-04 | 1999-09-28 | Ngk Insulators, Ltd. | Thermoelectric converter for heat-exchanger |
-
1981
- 1981-09-11 JP JP56143260A patent/JPS5844842A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0269158A1 (en) * | 1986-11-26 | 1988-06-01 | ITALTEL TELEMATICA S.p.A. | Digital telephone switching exchange, particularly for private systems (PABX) |
| US5959240A (en) * | 1996-12-04 | 1999-09-28 | Ngk Insulators, Ltd. | Thermoelectric converter for heat-exchanger |
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