JPS63219295A - Digital bus transmission switching system - Google Patents

Abstract

PURPOSE:To manage one unit of extension communication with two information channels, by detecting the delivery section of the information channel of an opposite extension terminal setting a frame bit as reference by the extension terminal, and receiving the bit of information of the delivery section by the terminal. CONSTITUTION:The extension terminal 14 (14A, 14B,...) detects the bit address of a frame setting the leading edge of a frame bit generated by a main device or a master machine 13 as reference by using a counter 8, and operates a timing generation circuit 7 based on the value of the counter 6. The circuit 7 generates the timings of a reception circuit 8 and a transmission circuit 9. A control circuit 11 decides a reception address bit section and a transmission address bit section based on a control data sent from the main device or the master machine 13 to the terminal 14 via a control channel bus. And the circuit 8 receives and takes out the bit of information of a reception section, and the circuit 9 transmits the bit of information to a transmission section. In such a way, it is possible to perform one unit of communication with two information channels without necessitating the distinction of a bit of incoming information from a bit of outgoing information.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a switching system in digital transmission in which a plurality of pieces of information such as voices and data are time-division multiplexed and transmitted.

[Conventional technology]

Figure 2 shows a system in which the extension system is bus-wired and extension terminals are connected. Multiple voices on bus 12.

Digital transmission systems that time-division multiplex and transmit data and other information have conventionally used a ping-pong transmission method that alternately transmits time-division transmission sections in which transmission information is multiplexed and reception sections in which reception information is multiplexed. .

FIG. 3 shows the frame structure of the conventional ping-pong transmission system. In the conventional method, when performing extension communication between the extension terminal 14A and the extension terminal 148, the extension terminal 14A and the extension terminal 1
48 puts information on the corresponding information channel of the transmission section. The main device or base unit 13 receives the information transmitted by the extension terminal 14A and the extension terminal 14B, and
The transmission information of the extension terminal 14A is transferred to the extension terminal 14 through the exchange circuit of
Then, the transmission information of extension terminal 148 must be transferred to the reception information of extension terminal 1-4A and then transmitted.

[Problem that the invention seeks to solve]

In the above-mentioned conventional technology, when performing extension communication between two extension terminals, in the upstream direction (extension terminal → main device or base unit 13
), and two information channels in the downstream direction (from the main unit or base unit 13 to the extension terminal), a total of four information channels are required, and there is a problem that many extension communication links cannot be established. there were. In addition, the main device or base unit 1
There was a problem in that the exchange circuit of No. 3 had to have hardware for returning and transmitting information. Furthermore, when applied to a home bus, there is a problem in that it is difficult to construct a distributed system in which information such as voice and data is processed only by extension terminals.

An object of the present invention is to solve such conventional problems and to reduce the number of information channels used when performing extension communication in a digital transmission system that time-division multiplexes and transmits multiple pieces of information such as voice and data on a bus. The purpose of the present invention is to provide a switching system in digital bus transmission that enables the reduction of hardware requirements for extension switching in the main device or base unit.

[Means for solving problems]

In order to solve the above-mentioned problems, the present invention connects a plurality of extension terminals by wiring the extension system to a main device or base unit that is connected to a central office line and has a circuit that generates frame bits. has an information channel and a control channel,
In a system that transmits digital signals to each channel, each extension terminal transmits upstream digital signals to the main device or base unit and downstream digital signals from the main unit or base unit, in the upstream and downstream directions. Regardless of the direction, according to the instructions on the control channel, the frame bits are sent as a reference to the information channels of the respective allocated sections, and each extension terminal, according to the instructions on the control channel, sends the frame bits as a reference, The feature is that the transmission section of the information channel of the other party's extension terminal is detected and the information of the transmission section is received.

[Effect]

In the present invention, an extension terminal connected to a digital transmission system that transmits using a bus transmits information to each assigned information channel based on frame bits generated by the main device or base device. It has a receiving circuit that can receive any information channel based on the frame bits, and when performing one-extension communication by mutually receiving information transmitted from other extension terminals, the main device or the parent There is no need for a switch circuit for exchanging extensions on the machine, and one extension communication can be realized with a total of two information channels without distinction between uplink and downlink information.

〔Example〕

FIG. 1 is a configuration diagram of an extension terminal showing an embodiment of the present invention.

In FIG. 1, 1 is a receiver that receives information such as voice and data, 2 is a driver that transmits information such as voice and data, 3 is a receiver that receives control signals, and 4 is a driver that transmits control signals. , 5 is a frame bit detection circuit that detects frame bits of an information channel (hereinafter referred to as Bch) frame that transmits information such as voice and data transmitted by the main device or base unit 13, and 6 is detected by the frame bit detection circuit 5. Based on the rising edge of the frame bit,
A bit counter that counts bit addresses with the precision of the master clock. 7 indicates the timing for transmitting information such as voice and data in the bit address interval assigned to the extension terminal based on the value of bit counter 6, and the bit assigned to the extension terminal. A timing generation circuit 8 generates the timing for receiving information such as voice and data within the address interval, and 8 is a timing generation circuit that generates the timing for receiving information such as voice and data within the frame received by receiver 1. A receiving circuit that detects information and takes in information such as voice and data of the assigned number of bits, 9 is a bit address assigned to the extension terminal based on the frame bits from which information such as voice and data to be transmitted is received. 10 is an input/output circuit that realizes a man-machine interface; 11 is a control channel (hereinafter referred to as Dch);
) Control signals received on the bus or input/output circuit 1
Based on the request from 0, the transmitting circuit 9. This is a control circuit that controls the receiving circuit 8 or creates a control signal to be transmitted.

The extension terminal 1.4 detects the frame bit generated by the main device or base unit 13 from the frame, uses the rising edge of the frame bit as a reference, detects the bit address of the frame using the bit counter 6, and reads the bit address of the bit counter 6. Based on the value, the timing generation circuit 7 is operated. The timing generating circuit 7 is connected to the receiving circuit 8. Generates timing for the transmitting circuit 9. The control circuit 11 is connected to the main device or base device 1.
Based on the control data sent from 3 to the extension terminal via the Dch bus, the reception address bit interval and the transmission address bit interval are determined, the reception circuit 8 receives and extracts the information of the reception interval, and the transmission circuit 9 transmits the information. Send information to the section.

FIG. 4 is an example of a frame configuration when the configuration shown in FIG. 1 is adopted. This shows an example in which 8 bits and 8 channels are allocated to the B bit.

Although the description of this example assumes transmission using the Manchester code, it goes without saying that the same operation is possible even if other codes such as AMI are used.

The bit address indicates the position of each bit in one frame, and the bit immediately after the frame bit is O, and there are up to 95 bits in order. Bit addresses 94.95 are frame bits. Bit addresses 0, 91 to 93 are guard bits before and after the frame bit. The bits that transmit Bah information (hereinafter referred to as B bits) are bit addresses 1-
90, and can take a plurality of BChs with a free bit length. Each Bch is separated by three guard bits.

FIG. 5 shows the extension terminal 14 using the frame structure shown in FIG.
A shows an example of frame usage when communication is performed between extension terminals 148, and the frame structure has no distinction between uplink and downlink.

−7= Next, establishing synchronization of extension terminals will be explained.

When the frame bits indicating frame synchronization, that is, the two bits V- and V+ shown in FIG. 4, arrive, the frame starts.

When the frame start can be determined, address 9 in Figure 4
Starting from the rising edge of bit 4, the 32nd clock (3rd bit) of the master clock is set to the value O of the bit counter 6. Bit counter 6 is 16 of the master clock
Count up by one for each tarotuku. In this example, one bit width corresponds to 16 master clock clocks. The value of bit counter 6 indicates the bit address within the frame.

Next, Bch transmission will be explained.

FIG. 6 is a procedure showing an example of bit address assignment. The bit that transmits Bch information is bit address 1.
~90, it can be freely divided and assigned to Bch. The Bch assignment is performed from the main device or base unit 13, and an appropriate bit address is assigned in response to a request from an extension terminal. In this example, Bch and B
Guard pits between channels are assigned 3 pits 1 and up.

FIG. 7 is an example of signal exchange in consideration of transmission delay on the bus 12. In this example, the guard pit will be explained as 3 bits. Main device or base unit 13 and extension terminal 14
When transmission is performed between the receiving circuits 8 and 8. It is assumed that the delay of the transmitting circuit 9 and the bus 12 can be tolerated up to τμs in a round trip.

The bit address interval assigned for transmission from the main device or base unit 13 to the extension terminal 14 is the B1 channel, and the bit address interval assigned for transmission from the extension terminal 14 to the main unit or base unit 13 is the B2 channel. do. In FIG. 7, the bit address section in this case is 8 bits. Further, the portion in the Hi-Z (high impedance) state corresponds to a guard pit.

FIG. 8 is an example of a transmission algorithm.

The extension terminal 14 transmits transmission information (transmission data) according to this transmission algorithm. In other words, bit addresses that can be output (allocated bit address range)
(801). If it is a bit address that can be output, output the bit group of the transmission data (802
). Note that before starting transmission, the main device or base unit 13 needs to allocate a bit address of the Bch section including the guard bit to be transmitted by the extension terminal.

Next, Bch reception will be explained.

FIG. 9 is an example of bit address allocation in reception. This shows an example where the extension terminal that transmits information and the extension terminal that receives information are installed close to each other and there is no phase difference due to transmission delay. Here, Hj-Z indicates high impedance.

Bch reception can be read in start-stop synchronization using a master clock as the reception timing from the beginning to the end of the assigned bit address and the immediately following guard pin 1-.

Each extension terminal sends (transmits Q information) to the other extension terminal based on the received frame bits V- and V+ generated by the main device or base unit 13.

FIG. 10 shows an example of bit address assignment for reception when the extension terminal that transmits information is installed far from the main device or base unit 13. here,
Hi-Z indicates high impedance.

In this case, an extension terminal that receives information is installed near the main device or base unit 13. Since the distance between the extension terminals is long, the delay time corresponding to this distance difference is X2=1.5 bits.

FIG. 11 is an example of a reception algorithm.

From the beginning of the allocated bit address (1101),
Reading starts in asynchronous format using the master clock, and data starts from the point where a change point occurs next to the high impedance state (1102, 1103), so it is possible to read a predetermined data pitch 1 to number. (110
4).

Note that before starting reception, the main device or base unit 13 needs to allocate a bit address for the Bch section that the extension terminal receives.

Since the configuration described above can be adopted, when performing one extension communication, it is possible to provide information with two information channels in total, and a switching circuit for performing extension communication is not required in the main device or base unit 13. It has the advantage of reducing the amount of hardware and reducing the number of information channels when providing the same service compared to the conventional technology.

Although the present embodiment has been described with respect to the case where Dch and Bch are separated, the case where Dch and Bch are multiplexed can also be realized in the same way. Further, although the extension terminal can receive any information channel, due to the condition of confidential communication, confidential communication can be ensured by permitting the information channel to be received under the control of the main device or base unit 13.

〔Effect of the invention〕

As explained above, according to the present invention, when performing extension communication, the number of information channels can be two. The number of information channels used is reduced to 1/2, which has the advantage of reducing the transmission bit rate or increasing the number of extension communications that can be communicated simultaneously at the same transmission bit rate.

Also, since there is no need to exchange upstream and downstream information,
It is possible to reduce the amount of hardware related to the switch circuit of the exchange circuit for performing extension communication in the main device or base unit, which has a large effect on cost reduction. Furthermore, since the transmission bit rate 1- is reduced, the influence of transmission waveform reflection at the extension terminal connection point is reduced, and the number of connected terminals can be increased. Furthermore, since frame bit transmission can be performed using a simple device, it is possible to construct a distributed system in which information such as voice and data is processed only by each extension terminal.

[Brief explanation of drawings]

Fig. 1 is a configuration diagram of an extension terminal showing an embodiment of the present invention, Fig. 2 is a system configuration diagram in which the extension terminal is connected to the extension system by bus wiring, and Fig. 3 is the frame configuration of a conventional ping-pong transmission system. 4 is a frame configuration diagram in an embodiment of the present invention, FIG. 5 is a diagram showing an example of frame usage that best expresses the features of the present invention, and FIG. 6 is a diagram showing a frame usage example that best represents the features of the present invention. Figure 7 shows the procedure for assigning bit addresses, Figure 7 shows the transmission delay between the main device or base unit and the extension terminal, Figure 8 shows the transmission algorithm, and Figure 9 shows the transmission delay between the extension terminals. FIG. 10 is a diagram showing the Bch reception timing when there is a phase difference between extension terminals due to transmission delay, and FIG. 11 is a diagram showing the reception algorithm. ]: Receiver, 2: Driver, 3: Receiver, 4: Driver, 5: Frame bit detection circuit, 6: Pitch 1 to counter, 7: Timing generation circuit, 8: Receiving circuit, 9: Transmitting circuit, IO = input/output circuit, 11: control circuit,] 2: bus, 13: main device or parent device, 14A, 14B,
i4□: Extension terminal. Patent applicant Nippon Telegraph and Telephone Corporation Figure 5 Figure 6

Claims (1)

[Claims] (1) Connect multiple extension terminals by wiring the extension system to a main unit or base unit that is connected to the central office line and has a circuit that generates frame bits, and provide an information channel and a control channel to the bus. , in a system that transmits digital signals to each channel, each extension terminal transmits an upstream digital signal to the main device or base unit and a downstream digital signal from the main unit or base unit,
Regardless of whether it is an uplink or a downlink, according to the instructions on the control channel, the frame bits are transmitted to the information channels of the allocated sections, and each extension terminal transmits the frame bits according to the instructions on the control channel. A switching system in digital bus transmission characterized by detecting a sending section of an information channel of a partner extension terminal based on , and receiving information on the sending section.